{"id":"https://openalex.org/W4205367793","doi":"https://doi.org/10.7873/date.2014.272","title":"Leakage-power-aware clock period minimization","display_name":"Leakage-power-aware clock period minimization","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W4205367793","doi":"https://doi.org/10.7873/date.2014.272"},"language":"en","primary_location":{"id":"doi:10.7873/date.2014.272","is_oa":false,"landing_page_url":"https://doi.org/10.7873/date.2014.272","pdf_url":null,"source":{"id":"https://openalex.org/S4363607957","display_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016707913","display_name":"Hua-Hsin Yeh","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hua-Hsin Yeh","raw_affiliation_strings":["Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060945705","display_name":"Shih-Hsu Huang","orcid":"https://orcid.org/0000-0001-8908-8384"},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Hsu Huang","raw_affiliation_strings":["Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113627821","display_name":"Yow-Tyng Nieh","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yow-Tyng Nieh","raw_affiliation_strings":["Information and Communications Research Labs, Industrial Technology Research Institute, Hsin Chu, Taiwan, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information and Communications Research Labs, Industrial Technology Research Institute, Hsin Chu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I4210148468"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.3931354,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.9147588014602661},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7170594334602356},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7140658497810364},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6852898001670837},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6645961999893188},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6083346009254456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5996449589729309},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5743707418441772},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5643442273139954},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.5004100799560547},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.45039102435112},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4420662522315979},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.43071386218070984},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4183283746242523},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4107131361961365},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3763936758041382},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.28523194789886475},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22260573506355286},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22220280766487122},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19828450679779053},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.19687747955322266},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19488400220870972},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.10851380228996277},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10372325778007507},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09280988574028015}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.9147588014602661},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7170594334602356},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7140658497810364},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6852898001670837},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6645961999893188},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6083346009254456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5996449589729309},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5743707418441772},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5643442273139954},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.5004100799560547},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.45039102435112},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4420662522315979},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.43071386218070984},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4183283746242523},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4107131361961365},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3763936758041382},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.28523194789886475},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22260573506355286},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22220280766487122},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19828450679779053},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.19687747955322266},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19488400220870972},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.10851380228996277},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10372325778007507},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09280988574028015},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.7873/date.2014.272","is_oa":false,"landing_page_url":"https://doi.org/10.7873/date.2014.272","pdf_url":null,"source":{"id":"https://openalex.org/S4363607957","display_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3006003651","https://openalex.org/W2040807843","https://openalex.org/W1564063853","https://openalex.org/W2133326759","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W4249038728","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766"],"abstract_inverted_index":{"In":[0,43],"the":[1,11,23,30,63,72,83,87,95,100,104,120,126,130],"design":[2],"of":[3,10,25,86,102,106,125],"nonzero":[4],"clock":[5,53,75,88,127],"skew":[6,76],"circuits,":[7],"an":[8],"increase":[9],"path":[12,27],"delay":[13,28],"may":[14],"improve":[15],"circuit":[16,33],"speed":[17,34],"and":[18,35,129],"reduce":[19],"leakage":[20,36,131],"power.":[21,132],"However,":[22],"impact":[24],"increasing":[26],"on":[29],"trade-off":[31],"between":[32],"power":[37],"has":[38,62],"not":[39],"been":[40],"well":[41],"studied.":[42],"this":[44],"paper,":[45],"we":[46],"propose":[47],"a":[48,110],"two-step":[49],"approach":[50,61,70,92,118],"for":[51],"leakage-power-aware":[52,74],"period":[54,128],"minimization.":[55],"Compared":[56],"with":[57,82],"previous":[58],"works,":[59],"our":[60,69,91,117],"following":[64],"two":[65],"significant":[66],"contributions.":[67],"First,":[68],"is":[71,93,109],"first":[73,96],"scheduling":[77],"that":[78,98,116],"can":[79],"guarantee":[80],"working":[81],"lower":[84],"bound":[85],"period.":[89],"Second,":[90],"also":[94],"work":[97],"demonstrates":[99],"problem":[101],"minimizing":[103],"number":[105],"extra":[107],"buffers":[108],"polynomial-time":[111],"problem.":[112],"Benchmark":[113],"data":[114],"show":[115],"achieves":[119],"best":[121],"results":[122],"in":[123],"terms":[124]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}