{"id":"https://openalex.org/W6911680426","doi":"https://doi.org/10.5281/zenodo.13950743","title":"Placement of Analog Integrated Circuits / Packing - synthetic instances","display_name":"Placement of Analog Integrated Circuits / Packing - synthetic instances","publication_year":2024,"publication_date":"2024-10-18","ids":{"openalex":"https://openalex.org/W6911680426","doi":"https://doi.org/10.5281/zenodo.13950743"},"language":"en","primary_location":{"id":"doi:10.5281/zenodo.13950743","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.13950743","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Dataset"},"type":"dataset","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.5281/zenodo.13950743","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Grus, Josef","orcid":"https://orcid.org/0000-0002-1136-370X"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Grus, Josef","raw_affiliation_strings":["Czech Technical University in Prague"],"raw_orcid":"https://orcid.org/0000-0002-1136-370X","affiliations":[{"raw_affiliation_string":"Czech Technical University in Prague","institution_ids":["https://openalex.org/I44504214"]}]},{"author_position":"last","author":{"id":null,"display_name":"Hanz\u00e1lek, Zden\u011bk","orcid":"https://orcid.org/0000-0002-8135-1296"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Hanz\u00e1lek, Zden\u011bk","raw_affiliation_strings":["Czech Technical University in Prague"],"raw_orcid":"https://orcid.org/0000-0002-8135-1296","affiliations":[{"raw_affiliation_string":"Czech Technical University in Prague","institution_ids":["https://openalex.org/I44504214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I44504214"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":null,"topics":[],"keywords":[{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6060000061988831},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5949000120162964},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.5892000198364258},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5090000033378601},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4912000000476837},{"id":"https://openalex.org/keywords/constructive","display_name":"Constructive","score":0.45210000872612},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4503999948501587},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.4422000050544739},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.390500009059906}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6380000114440918},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6060000061988831},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5949000120162964},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.5892000198364258},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5090000033378601},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4912000000476837},{"id":"https://openalex.org/C2778701210","wikidata":"https://www.wikidata.org/wiki/Q28130034","display_name":"Constructive","level":3,"score":0.45210000872612},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4503999948501587},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.4422000050544739},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.390500009059906},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.3506999909877777},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.34279999136924744},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.3391999900341034},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3336000144481659},{"id":"https://openalex.org/C188032258","wikidata":"https://www.wikidata.org/wiki/Q1128371","display_name":"Constructive solid geometry","level":2,"score":0.31869998574256897},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.2953000068664551},{"id":"https://openalex.org/C43592290","wikidata":"https://www.wikidata.org/wiki/Q12148490","display_name":"Placer mining","level":2,"score":0.290800005197525},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2874999940395355},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.2842999994754791},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2824999988079071},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.27219998836517334},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2556999921798706},{"id":"https://openalex.org/C88230418","wikidata":"https://www.wikidata.org/wiki/Q131476","display_name":"Graph theory","level":2,"score":0.25200000405311584}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.5281/zenodo.13950743","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.13950743","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Dataset"}],"best_oa_location":{"id":"doi:10.5281/zenodo.13950743","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.13950743","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Dataset"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41228124499320984}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Synthetically":[0],"generated":[1],"instances":[2],"used":[3],"in":[4],"Automatic":[5],"Placer":[6],"for":[7,23],"Analog":[8,27],"Circuits":[9,29],"Using":[10],"Integer":[11],"Linear":[12],"Programming":[13],"Warm":[14],"Started":[15],"by":[16],"Graph":[17],"Drawing":[18],"10.5220/0011789300003396":[19],"Matheuristic":[20],"Local":[21],"Search":[22],"the":[24],"Placement":[25],"of":[26,33],"Integrated":[28],"10.1007/978-3-031-49662-2_10":[30],"Automated":[31],"placement":[32],"analog":[34],"integrated":[35],"circuits":[36],"using":[37],"priority-based":[38],"constructive":[39],"heuristic":[40],"papers":[41],"10.1016/j.cor.2024.106643":[42]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2025-10-10T00:00:00"}