{"id":"https://openalex.org/W1969247401","doi":"https://doi.org/10.5220/0005057407260733","title":"Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures","display_name":"Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W1969247401","doi":"https://doi.org/10.5220/0005057407260733","mag":"1969247401"},"language":"en","primary_location":{"id":"doi:10.5220/0005057407260733","is_oa":false,"landing_page_url":"https://doi.org/10.5220/0005057407260733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 11th International Conference on Informatics in Control, Automation and Robotics","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083391397","display_name":"Christoforos Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Christoforos Economakos","raw_affiliation_strings":["Technological Educational Institution of Sterea Ellada, Greece","Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece"],"affiliations":[{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece","institution_ids":["https://openalex.org/I51955386"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016630838","display_name":"M. G. Skarpetis","orcid":"https://orcid.org/0000-0002-4252-6305"},"institutions":[{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Michael Skarpetis","raw_affiliation_strings":["Technological Educational Institution of Sterea Ellada, Greece","Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece"],"affiliations":[{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece","institution_ids":["https://openalex.org/I51955386"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089110665","display_name":"George Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Economakos","raw_affiliation_strings":["National Technical University of Athens, Greece","National Technical University of Athens, School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR15780 Zografou, Greece"],"affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"National Technical University of Athens, School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR15780 Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5083391397"],"corresponding_institution_ids":["https://openalex.org/I51955386"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.04887351,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"726","last_page":"733"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7258057594299316},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6930148005485535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6735851764678955},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6564309597015381},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6127285957336426},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5581315755844116},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4886813461780548},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44237253069877625},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.438416063785553},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.41552361845970154},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4115782678127289},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2935326099395752},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20836558938026428},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.16812431812286377},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08664652705192566}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7258057594299316},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6930148005485535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6735851764678955},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6564309597015381},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6127285957336426},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5581315755844116},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4886813461780548},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44237253069877625},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.438416063785553},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.41552361845970154},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4115782678127289},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2935326099395752},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20836558938026428},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.16812431812286377},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08664652705192566},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.5220/0005057407260733","is_oa":false,"landing_page_url":"https://doi.org/10.5220/0005057407260733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 11th International Conference on Informatics in Control, Automation and Robotics","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321038","display_name":"Fonds National de la Recherche Luxembourg","ror":"https://ror.org/039z13y21"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1604677972","https://openalex.org/W1691307101","https://openalex.org/W2006932449","https://openalex.org/W2007222857","https://openalex.org/W2021882684","https://openalex.org/W2056302270","https://openalex.org/W2060943953","https://openalex.org/W2064057042","https://openalex.org/W2094998159","https://openalex.org/W2100183523","https://openalex.org/W2129788823","https://openalex.org/W2150562785","https://openalex.org/W2157505081","https://openalex.org/W2163226520","https://openalex.org/W2182349853","https://openalex.org/W2539591775","https://openalex.org/W2543206222"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2743305891","https://openalex.org/W4385309418","https://openalex.org/W1490270176","https://openalex.org/W2148101730","https://openalex.org/W2097806352","https://openalex.org/W2210370345"],"abstract_inverted_index":{"Digital":[0,49],"design":[1,71,75,87,93,100,109,133],"has":[2,27],"been":[3,41],"growing":[4],"rapidly":[5],"during":[6],"the":[7,118,132,139,156,171],"last":[8],"years,":[9],"offering":[10,163],"advanced":[11],"implementation":[12,66,150],"solutions":[13],"for":[14,117,185],"a":[15,28,108,124,179],"diversity":[16],"of":[17,120,134,141],"appliances":[18],"and":[19,24,76,101,114,148,166,174],"instruments,":[20],"integrating":[21],"different":[22],"sensors":[23],"actuators.":[25],"This":[26,105],"great":[29],"impact":[30],"on":[31],"embedded":[32,161],"automation,":[33],"where":[34],"traditional":[35],"Programmable":[36,60],"Logic":[37],"Controllers":[38],"(PLCs)":[39],"have":[40],"gradually":[42],"replaced":[43],"by":[44,91],"high":[45,181],"performance":[46,164],"Embedded":[47],"Controllers,":[48],"Signal":[50],"Processor":[51],"(DSP)":[52],"chips":[53],"and,":[54],"more":[55],"recently,":[56],"power":[57],"efficient":[58,70],"Field":[59],"Gate":[61],"Arrays":[62],"(FPGAs).":[63],"Such":[64],"new":[65,86,92,135],"platforms":[67],"bring":[68],"together":[69],"methodologies,":[72],"like":[73,95],"model-based":[74,115],"high-level":[77],"or":[78,138],"C":[79],"level":[80],"program-based":[81,113],"design.":[82],"In":[83],"their":[84],"turn,":[85],"methodologies":[88],"are":[89,152],"accompanied":[90],"technologies":[94],"Intellectual":[96],"Property":[97],"(IP)":[98],"based":[99],"High-Level":[102],"Synthesis":[103],"(HLS).":[104],"paper":[106],"presents":[107],"environment":[110],"that":[111,129],"utilizes":[112],"design,":[116],"development":[119],"PLC":[121],"applications.":[122],"Specifically,":[123],"tool":[125,176],"flow":[126,177],"is":[127],"constructed":[128],"supports":[130],"either":[131],"control":[136,187],"algorithms":[137,143,158],"translation":[140],"existing":[142],"into":[144],"C.":[145],"Then,":[146],"HLS":[147],"FPGA":[149],"tools":[151],"adopted,":[153],"to":[154],"implement":[155],"selected":[157],"as":[159],"multicore,":[160],"designs,":[162],"improvements":[165],"hardware":[167],"utilization":[168],"efficiency.":[169],"Overall,":[170],"proposed":[172],"methodology":[173],"underlying":[175],"support":[178],"novel":[180],"productivity":[182],"prototyping":[183],"platform":[184],"digital":[186],"applications,":[188],"with":[189],"very":[190],"promising":[191],"future":[192],"extension":[193],"capabilities.":[194]},"counts_by_year":[{"year":2022,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}