{"id":"https://openalex.org/W2461129535","doi":"https://doi.org/10.5075/epfl-thesis-7004","title":"FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages","display_name":"FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2461129535","doi":"https://doi.org/10.5075/epfl-thesis-7004","mag":"2461129535"},"language":"en","primary_location":{"id":"pmh:oai:infoscience.tind.io:218533","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/126305","pdf_url":"https://infoscience.epfl.ch/record/218533/files/EPFL_TH7004.pdf","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"doctoral thesis"},"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/record/218533/files/EPFL_TH7004.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012088918","display_name":"Nithin V. George","orcid":"https://orcid.org/0000-0002-7131-7238"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"George, Nithin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5012088918"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8063707947731018},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.673145055770874},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.636150062084198},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.6020793914794922},{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.5861812233924866},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5685580372810364},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5546193718910217},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.537659227848053},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.530935525894165},{"id":"https://openalex.org/keywords/digital-subscriber-line","display_name":"Digital subscriber line","score":0.44643154740333557},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.433156818151474},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.41277170181274414},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3978545665740967},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35742974281311035},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.19200217723846436},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16147050261497498}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8063707947731018},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.673145055770874},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.636150062084198},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.6020793914794922},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.5861812233924866},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5685580372810364},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5546193718910217},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.537659227848053},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.530935525894165},{"id":"https://openalex.org/C201374245","wikidata":"https://www.wikidata.org/wiki/Q104534","display_name":"Digital subscriber line","level":2,"score":0.44643154740333557},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.433156818151474},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.41277170181274414},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3978545665740967},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35742974281311035},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.19200217723846436},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16147050261497498},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"pmh:oai:infoscience.tind.io:218533","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/126305","pdf_url":"https://infoscience.epfl.ch/record/218533/files/EPFL_TH7004.pdf","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"doctoral thesis"},{"id":"pmh:doi:10.5075/epfl-thesis-7004","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doctoral thesis"},{"id":"pmh:oai:infoscience.epfl.ch:218533","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/218533","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"doi:10.5075/epfl-thesis-7004","is_oa":true,"landing_page_url":"https://doi.org/10.5075/epfl-thesis-7004","pdf_url":null,"source":{"id":"https://openalex.org/S4306400488","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Dissertation"},{"id":"mag:2461129535","is_oa":false,"landing_page_url":"https://infoscience.epfl.ch/record/218533","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"pmh:oai:infoscience.tind.io:218533","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/126305","pdf_url":"https://infoscience.epfl.ch/record/218533/files/EPFL_TH7004.pdf","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"doctoral thesis"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":false},"content_urls":{"pdf":"https://content.openalex.org/works/W2461129535.pdf"},"referenced_works_count":70,"referenced_works":["https://openalex.org/W42313609","https://openalex.org/W294835284","https://openalex.org/W1493893823","https://openalex.org/W1495226832","https://openalex.org/W1516659258","https://openalex.org/W1530279678","https://openalex.org/W1536721241","https://openalex.org/W1545099940","https://openalex.org/W1548991402","https://openalex.org/W1600324942","https://openalex.org/W1627547140","https://openalex.org/W1631634011","https://openalex.org/W1665874673","https://openalex.org/W1961751213","https://openalex.org/W1964471912","https://openalex.org/W1978924650","https://openalex.org/W1984222112","https://openalex.org/W1994154443","https://openalex.org/W1995783993","https://openalex.org/W2000921084","https://openalex.org/W2005022399","https://openalex.org/W2008070495","https://openalex.org/W2009541799","https://openalex.org/W2016688446","https://openalex.org/W2018055497","https://openalex.org/W2024381286","https://openalex.org/W2030898836","https://openalex.org/W2036529651","https://openalex.org/W2059712825","https://openalex.org/W2066671865","https://openalex.org/W2071630526","https://openalex.org/W2075160498","https://openalex.org/W2076257979","https://openalex.org/W2083986012","https://openalex.org/W2085884196","https://openalex.org/W2087852986","https://openalex.org/W2088675571","https://openalex.org/W2091338501","https://openalex.org/W2094756095","https://openalex.org/W2094998159","https://openalex.org/W2095761111","https://openalex.org/W2102562397","https://openalex.org/W2103431534","https://openalex.org/W2103798154","https://openalex.org/W2112432448","https://openalex.org/W2112678088","https://openalex.org/W2123092976","https://openalex.org/W2125543909","https://openalex.org/W2127699991","https://openalex.org/W2131023841","https://openalex.org/W2133156997","https://openalex.org/W2138163628","https://openalex.org/W2141597697","https://openalex.org/W2141919235","https://openalex.org/W2143609451","https://openalex.org/W2147578933","https://openalex.org/W2148740615","https://openalex.org/W2153185479","https://openalex.org/W2154991996","https://openalex.org/W2160183719","https://openalex.org/W2160955218","https://openalex.org/W2166029537","https://openalex.org/W2168113051","https://openalex.org/W2171429297","https://openalex.org/W2173213060","https://openalex.org/W2263852834","https://openalex.org/W2343695530","https://openalex.org/W2612093424","https://openalex.org/W3009458112","https://openalex.org/W3172349748"],"related_works":["https://openalex.org/W2906737788","https://openalex.org/W1976372309","https://openalex.org/W2462268631","https://openalex.org/W2159246592","https://openalex.org/W1608821582","https://openalex.org/W1997633104","https://openalex.org/W2034022664","https://openalex.org/W2054414374","https://openalex.org/W2109046561","https://openalex.org/W2889341445","https://openalex.org/W282396022","https://openalex.org/W2135999361","https://openalex.org/W3099952554","https://openalex.org/W1487037667","https://openalex.org/W2938737185","https://openalex.org/W2264308146","https://openalex.org/W2036739012","https://openalex.org/W2011559083","https://openalex.org/W2132993912","https://openalex.org/W2058549609"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"have":[5,231],"the":[6,97,106,128,153,280,301,310,358,362,388,392,406,418,429,440],"unique":[7],"ability":[8],"to":[9,19,26,56,95,114,151,171,193,230,235,241,248,256,326,331,347,355,380,395,422,427,449],"be":[10,288],"configured":[11],"into":[12,304,337],"application-specific":[13],"architectures":[14],"that":[15,32,73,278],"are":[16,54,275],"well":[17,262,365],"suited":[18],"specific":[20],"computing":[21,446],"problems.":[22],"This":[23],"enables":[24],"them":[25,336],"achieve":[27,384],"performances":[28],"and":[29,46,63,101,117,131,155,190,197,216,271,284,286,291,308,323,334,376,400,414],"energy":[30],"efficiencies":[31],"outclass":[33],"other":[34],"processor-based":[35],"architectures,":[36],"such":[37,135,266,315,402],"as":[38,267,316,364,366],"Chip":[39],"Multiprocessors":[40],"(CMPs),":[41],"Graphic":[42],"Processing":[43],"Units":[44],"(GPUs)":[45],"Digital":[47],"Signal":[48],"Processors":[49],"(DSPs).":[50],"Despite":[51],"this,":[52,385],"FPGAs":[53],"yet":[55],"gain":[57],"widespread":[58],"adoption,":[59],"especially":[60],"among":[61],"application":[62,70,80,143,450],"software":[64],"developers,":[65],"because":[66],"of":[67,105,133,157,282,312,318,361,391,432,443],"their":[68],"laborious":[69],"development":[71],"process":[72],"requires":[74],"hardware":[75,83,99,120,160,174,221,232,245,259,329,353],"design":[76,233,246],"expertise.":[77],"In":[78,145,296,434],"some":[79],"areas,":[81],"domain-specific":[82,136,159,250],"synthesis":[84,161,222,226],"tools":[85,110,137,227],"alleviate":[86],"this":[87,123,146,209,435,437],"problem":[88,442],"by":[89,211,371,412],"using":[90],"a":[91,169,182,195,200,254,338],"Domain-Specific":[92],"Language":[93],"(DSL)":[94],"hide":[96],"low-level":[98],"details":[100],"also":[102],"improve":[103],"productivity":[104],"developer.":[107],"Additionally,":[108],"these":[109,313],"leverage":[111],"domain":[112],"knowledge":[113,234],"perform":[115],"optimizations":[116],"produce":[118,236],"high-quality":[119,237,258,328],"designs.":[121],"While":[122],"approach":[124,186],"holds":[125],"great":[126],"promise,":[127],"significant":[129],"effort":[130,154],"cost":[132,156],"developing":[134,158],"make":[138],"it":[139,218],"unaffordable":[140],"in":[141,181,199],"many":[142],"areas.":[144],"thesis,":[147],"we":[148,167,207,252,299,343,386],"develop":[149,168,194,208,249,253],"techniques":[150],"reduce":[152,205,270],"tools.":[162,223],"To":[163,203,383],"demonstrate":[164],"our":[165,185,297,345],"approach,":[166,298],"toolchain":[170],"generate":[172,257,327,401],"complete":[173,339],"systems":[175],"from":[176,261,357,405],"high-level":[177,408],"functional":[178,409],"specifications":[179,303],"written":[180],"DSL.":[183],"Firstly,":[184],"uses":[187],"language":[188],"embedding":[189],"type-directed":[191],"staging":[192],"DSL":[196,302],"compiler":[198,210],"cost-effective":[201],"manner.":[202],"further":[204],"effort,":[206],"composing":[212],"reusable":[213],"optimization":[214],"modules,":[215],"integrate":[217],"with":[219],"existing":[220],"However,":[224],"most":[225],"require":[228],"users":[229],"results.":[238],"Therefore,":[239],"secondly,":[240],"facilitate":[242],"people":[243],"without":[244,293],"skills":[247],"tools,":[251],"methodology":[255,346],"designs":[260,404],"known":[263],"computational":[264,273,306,393,430],"patterns,":[265,314],"map,":[268],"zipWith,":[269],"foreach;":[272],"patterns":[274,307,375,394],"algorithmic":[276],"methods":[277],"capture":[279],"nature":[281],"computation":[283],"communication":[285],"can":[287],"easily":[289],"understood":[290],"used":[292],"expert":[294],"knowledge.":[295],"decompose":[300],"constituent":[305],"exploit":[309],"properties":[311,390],"degree":[317],"parallelism,":[319],"interdependence":[320],"between":[321],"operations":[322],"data-access":[324,389],"characteristics,":[325],"modules":[330,354],"implement":[332],"them,":[333],"compose":[335],"system":[340],"design.":[341],"Lastly,":[342],"extended":[344],"automatically":[348,396],"parallelize":[349],"computations":[350],"across":[351],"multiple":[352],"benefit":[356],"spatial":[359],"parallelism":[360],"FPGA":[363],"overcome":[367],"performance":[368,415],"problems":[369],"caused":[370],"non-sequential":[372],"data":[373],"access":[374,378],"long":[377],"latency":[379],"external":[381],"memory.":[382],"utilize":[387],"identify":[397],"synchronization":[398],"requirements":[399],"multi-module":[403],"same":[407],"specifications.":[410],"Driven":[411],"power":[413],"constraints,":[416],"today":[417],"world":[419],"is":[420],"turning":[421],"reconfigurable":[423],"technology":[424],"(i.e.,":[425],"FPGAs)":[426],"meet":[428],"needs":[431],"tomorrow.":[433],"light,":[436],"work":[438],"addresses":[439],"cardinal":[441],"making":[444],"tomorrow's":[445],"infrastructure":[447],"programmable":[448],"developers.":[451]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2025-10-10T00:00:00"}