{"id":"https://openalex.org/W7169845090","doi":"https://doi.org/10.48550/arxiv.2607.18141","title":"A CXL Memory Rack for Multi-Turn LLM Serving","display_name":"A CXL Memory Rack for Multi-Turn LLM Serving","publication_year":2026,"publication_date":"2026-07-20","ids":{"openalex":"https://openalex.org/W7169845090","doi":"https://doi.org/10.48550/arxiv.2607.18141"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2607.18141","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2607.18141","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2607.18141","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063686935","display_name":"Hakbeom Jang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jang, Hakbeom","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103647655","display_name":"In\u2010Ok Song","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Song, Inho","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008944433","display_name":"Hoshik Kim","orcid":"https://orcid.org/0000-0002-4017-8124"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kim, Hoshik","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070346739","display_name":"Sam H. Noh","orcid":"https://orcid.org/0000-0002-9152-0321"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Noh, Sam H.","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5145970945","display_name":"Jongryool Kim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kim, Jongryool","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7757999897003174,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7757999897003174,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.18279999494552612,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.011300000362098217,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7972999811172485},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.7468000054359436},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7361000180244446},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5591999888420105},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.53329998254776},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.44110000133514404},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.37209999561309814},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.3490000069141388}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8145999908447266},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7972999811172485},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.7468000054359436},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7361000180244446},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5591999888420105},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.53329998254776},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.447299987077713},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.44110000133514404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4244000017642975},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.37209999561309814},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.3490000069141388},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.34060001373291016},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3361999988555908},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.3237999975681305},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.3165999948978424},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3149999976158142},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.31470000743865967},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2888000011444092},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.27309998869895935},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.2687000036239624},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.2646999955177307},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.25619998574256897},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.25429999828338623}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2607.18141","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2607.18141","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2607.18141","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2607.18141","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Long-context,":[0],"multi-turn,":[1],"and":[2,31,41,105,130,159,177],"agentic":[3],"LLM":[4,72],"workloads":[5],"increasingly":[6],"reuse":[7,13,21],"previously":[8],"processed":[9],"context,":[10],"making":[11],"KV-cache":[12,110,143],"essential":[14],"for":[15,70],"reducing":[16],"redundant":[17],"computation.":[18],"However,":[19],"this":[20],"shifts":[22],"the":[23,26,76,102,164],"bottleneck":[24],"to":[25,47,49,118,134],"memory":[27,68,77,82],"tier":[28],"that":[29],"stores":[30],"serves":[32],"reusable":[33],"KV":[34,123],"states":[35],"at":[36,145],"cluster":[37],"scale.":[38],"GPU":[39],"HBM":[40],"host":[42],"DRAM":[43,91,114,166],"are":[44],"too":[45],"costly":[46],"scale":[48],"TB-scale":[50,121],"shared":[51],"context":[52],"capacity,":[53],"motivating":[54],"remote":[55],"tiers":[56],"built":[57],"from":[58],"lower-cost,":[59],"higher-capacity":[60],"media.":[61],"This":[62],"paper":[63],"presents":[64],"HyMCache,":[65],"a":[66,86,97,152],"CXL":[67,98],"rack":[69,78],"multi-turn":[71,109],"serving.":[73,181],"We":[74,148],"build":[75],"using":[79],"cost-efficient":[80],"CXL-hybrid":[81],"(CXL-HM),":[83],"which":[84],"combines":[85],"small":[87],"amount":[88],"of":[89,108],"in-device":[90],"with":[92,183],"large":[93],"SSD-backed":[94,122],"capacity":[95],"behind":[96],"interface.":[99],"By":[100],"exploiting":[101],"read-dominant,":[103],"predictable,":[104],"append-only":[106],"nature":[107],"access,":[111],"HyMCache":[112,150,168,188],"rethinks":[113],"management":[115],"within":[116],"CXL-HM":[117,154],"efficiently":[119],"support":[120],"reuse.":[124],"It":[125],"uses":[126,195],"request-level":[127],"prefix":[128],"prefetching":[129],"opportunistic":[131],"write":[132],"buffering":[133],"stage":[135],"latency-critical":[136],"reads":[137],"in":[138,174,179],"device":[139],"DRAM,":[140],"enabling":[141],"DRAM-scale":[142],"efficiency":[144],"SSD-level":[146],"cost.":[147],"evaluate":[149],"on":[151],"real":[153],"prototype":[155],"under":[156],"both":[157],"single-aggregator":[158],"PD-disaggregated":[160,180],"serving":[161,176],"configurations.":[162],"Under":[163],"same":[165],"budget,":[167],"outperforms":[169],"local":[170],"LMCache":[171],"by":[172],"3.0x":[173],"single-node":[175],"1.45x":[178],"Compared":[182],"1":[184],"TB":[185],"distributed-DRAM":[186],"Mooncake,":[187],"incurs":[189],"about":[190],"30%":[191],"lower":[192],"performance":[193],"but":[194],"16x":[196],"less":[197],"DRAM.":[198]},"counts_by_year":[],"updated_date":"2026-08-08T07:41:36.138363","created_date":"2026-07-22T00:00:00"}
