{"id":"https://openalex.org/W7166012077","doi":"https://doi.org/10.48550/arxiv.2606.27319","title":"An Instruction Set Architecture for IMPLY-based Memristive Processing-in-Array","display_name":"An Instruction Set Architecture for IMPLY-based Memristive Processing-in-Array","publication_year":2026,"publication_date":"2026-06-25","ids":{"openalex":"https://openalex.org/W7166012077","doi":"https://doi.org/10.48550/arxiv.2606.27319"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.27319","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.27319","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.27319","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5139452690","display_name":"Liam Splittgerber","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Splittgerber, Liam","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004122681","display_name":"Fabian Seiler","orcid":"https://orcid.org/0009-0000-6517-451X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Seiler, Fabian","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5050080301","display_name":"Nima TaheriNejad","orcid":"https://orcid.org/0000-0002-1295-0332"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"TaheriNejad, Nima","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9598000049591064,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9598000049591064,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.009200000204145908,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.002300000051036477,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.6141999959945679},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.5800999999046326},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5049999952316284},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.498199999332428},{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.49709999561309814},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.4853000044822693},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.42640000581741333},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4185999929904938},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.39739999175071716}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.75},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.6141999959945679},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.5800999999046326},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5049999952316284},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.498199999332428},{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.49709999561309814},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.4853000044822693},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45669999718666077},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.42640000581741333},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4185999929904938},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.39739999175071716},{"id":"https://openalex.org/C2778456923","wikidata":"https://www.wikidata.org/wiki/Q5337692","display_name":"Edge computing","level":3,"score":0.38909998536109924},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3878999948501587},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.38420000672340393},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.3659999966621399},{"id":"https://openalex.org/C23375383","wikidata":"https://www.wikidata.org/wiki/Q176499","display_name":"Unconventional computing","level":2,"score":0.33970001339912415},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.3246999979019165},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.31679999828338623},{"id":"https://openalex.org/C154240960","wikidata":"https://www.wikidata.org/wiki/Q2860294","display_name":"Database-centric architecture","level":5,"score":0.29269999265670776},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.289900004863739},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.2865999937057495},{"id":"https://openalex.org/C101518730","wikidata":"https://www.wikidata.org/wiki/Q930236","display_name":"Energy harvesting","level":3,"score":0.2842999994754791},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.2833000123500824},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.2827000021934509},{"id":"https://openalex.org/C138236772","wikidata":"https://www.wikidata.org/wiki/Q25098575","display_name":"Edge device","level":3,"score":0.2809000015258789},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27469998598098755},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.27469998598098755},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C52146309","wikidata":"https://www.wikidata.org/wiki/Q7431116","display_name":"Schema (genetic algorithms)","level":2,"score":0.2621000111103058},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25850000977516174},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.25040000677108765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.27319","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.27319","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.27319","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.27319","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0],"push":[1],"towards":[2],"expanded":[3],"ultra-low-power":[4,103],"edge":[5,104],"computing":[6],"necessitates":[7],"hardware":[8],"capable":[9],"of":[10,68,88,125,158,170,177],"operating":[11],"under":[12],"extremely":[13],"strict":[14],"energy":[15,152],"constraints.":[16],"Traditional":[17],"Complementary":[18],"Metal-Oxide-Semiconductor":[19],"(CMOS)":[20],"microcontrollers":[21],"are":[22,162],"fundamentally":[23],"limited":[24],"in":[25,141,195],"this":[26],"domain":[27],"by":[28,34,54],"the":[29,35,66,69,86,113,117,126,133,142,151,159,174,178,189],"von":[30],"Neumann":[31],"bottleneck":[32],"and":[33,58,132,154,166],"static":[36],"power":[37],"leakage":[38],"inherent":[39],"to":[40,51,77,138],"volatile":[41],"memory.":[42],"Memristive":[43],"In-Memory":[44],"Computing":[45],"(IMC)":[46],"offers":[47],"a":[48,61,79,122],"promising":[49],"solution":[50],"these":[52],"inefficiencies":[53],"unifying":[55],"data":[56],"storage":[57],"computation":[59,140],"into":[60],"single":[62],"non-volatile":[63],"component.":[64],"However,":[65],"State":[67],"Art":[70],"(SoA)":[71],"predominantly":[72],"focuses":[73],"on":[74],"accelerators":[75],"designed":[76],"be":[78,193],"co-processor":[80],"for":[81,102],"data-intensive":[82],"computation.":[83],"This":[84,95],"leaves":[85],"prospect":[87],"standalone,":[89],"general-purpose":[90],"IMC":[91],"microcontroller":[92],"architectures":[93],"underexplored.":[94],"thesis":[96],"proposes":[97],"such":[98],"an":[99,107,183,196],"architecture":[100,161],"tailored":[101],"devices,":[105],"alongside":[106],"instruction":[108,128],"set":[109,129],"closely":[110],"derived":[111],"from":[112],"RV32I":[114],"standard.":[115],"Using":[116],"IMPLY":[118],"stateful":[119],"logic":[120],"paradigm,":[121],"complete":[123],"implementation":[124],"proposed":[127,160,190],"is":[130,146,180],"provided,":[131],"novel":[134],"addressing":[135],"schema":[136],"required":[137],"support":[139],"memristive":[143],"crossbar":[144],"array":[145],"described":[147],"as":[148],"well.":[149],"Then,":[150],"use":[153],"other":[155],"circuit-level":[156],"metrics":[157],"evaluated":[163],"through":[164,182],"simulation":[165],"compared":[167],"against":[168],"those":[169],"traditional":[171],"microcontrollers.":[172],"Finally,":[173],"functional":[175],"viability":[176],"design":[179,191],"demonstrated":[181],"application":[184],"case":[185],"study,":[186],"describing":[187],"how":[188],"could":[192],"used":[194],"intelligent":[197],"environmental":[198],"sensor":[199],"node.":[200]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-06-27T00:00:00"}
