{"id":"https://openalex.org/W7165777591","doi":"https://doi.org/10.48550/arxiv.2606.23941","title":"BipBipCache: Pipeline-Aware Integration of Low-Latency Tweakable Encryption in an Embedded Cache Controller","display_name":"BipBipCache: Pipeline-Aware Integration of Low-Latency Tweakable Encryption in an Embedded Cache Controller","publication_year":2026,"publication_date":"2026-06-22","ids":{"openalex":"https://openalex.org/W7165777591","doi":"https://doi.org/10.48550/arxiv.2606.23941"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.23941","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.23941","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.23941","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5139260438","display_name":"Corbin Hibler","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hibler, Corbin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124175741","display_name":"Firas Hassan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hassan, Firas","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5094330935","display_name":"Eric McKanna","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"McKanna, Eric","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.6531999707221985,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.6531999707221985,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.3239000141620636,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.006200000178068876,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.6233999729156494},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.585099995136261},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.4399000108242035},{"id":"https://openalex.org/keywords/block-cipher","display_name":"Block cipher","score":0.42820000648498535},{"id":"https://openalex.org/keywords/cipher","display_name":"Cipher","score":0.41510000824928284},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.41510000824928284},{"id":"https://openalex.org/keywords/ciphertext","display_name":"Ciphertext","score":0.4097000062465668},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.38999998569488525},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.38690000772476196},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3806000053882599}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7778000235557556},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6477000117301941},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.6233999729156494},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.585099995136261},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4878999888896942},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.4399000108242035},{"id":"https://openalex.org/C106544461","wikidata":"https://www.wikidata.org/wiki/Q543151","display_name":"Block cipher","level":3,"score":0.42820000648498535},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.41510000824928284},{"id":"https://openalex.org/C2780221543","wikidata":"https://www.wikidata.org/wiki/Q4681865","display_name":"Cipher","level":3,"score":0.41510000824928284},{"id":"https://openalex.org/C93974786","wikidata":"https://www.wikidata.org/wiki/Q1589480","display_name":"Ciphertext","level":3,"score":0.4097000062465668},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.38999998569488525},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.38690000772476196},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3806000053882599},{"id":"https://openalex.org/C9368797","wikidata":"https://www.wikidata.org/wiki/Q117010","display_name":"Disk encryption","level":4,"score":0.3750999867916107},{"id":"https://openalex.org/C94520183","wikidata":"https://www.wikidata.org/wiki/Q190746","display_name":"Advanced Encryption Standard","level":3,"score":0.3709000051021576},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.37049999833106995},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.34709998965263367},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.32030001282691956},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.31929999589920044},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.30959999561309814},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.3082999885082245},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.29280000925064087},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.2924000024795532},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.2799000144004822},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2777999937534332},{"id":"https://openalex.org/C61719626","wikidata":"https://www.wikidata.org/wiki/Q17081362","display_name":"Disk encryption hardware","level":5,"score":0.27390000224113464},{"id":"https://openalex.org/C33884865","wikidata":"https://www.wikidata.org/wiki/Q1254335","display_name":"Cryptographic protocol","level":3,"score":0.26809999346733093},{"id":"https://openalex.org/C71745522","wikidata":"https://www.wikidata.org/wiki/Q2476929","display_name":"Confidentiality","level":2,"score":0.26570001244544983},{"id":"https://openalex.org/C203062551","wikidata":"https://www.wikidata.org/wiki/Q201339","display_name":"Public-key cryptography","level":3,"score":0.26010000705718994},{"id":"https://openalex.org/C92717368","wikidata":"https://www.wikidata.org/wiki/Q1162538","display_name":"Plaintext","level":3,"score":0.25920000672340393},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.2558000087738037},{"id":"https://openalex.org/C148417208","wikidata":"https://www.wikidata.org/wiki/Q4825882","display_name":"Authentication (law)","level":2,"score":0.2531000077724457},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.25040000677108765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.23941","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.23941","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.23941","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.23941","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Consumer":[0],"and":[1,49,76,98,128,143,172],"embedded":[2],"processors":[3],"store":[4],"sensitive":[5],"data":[6,48],"in":[7,24,51],"on-chip":[8],"SRAM":[9,99],"caches":[10],"that":[11,37,107],"remain":[12],"readable":[13],"after":[14,137],"power":[15],"loss":[16],"or":[17],"physical":[18],"probing":[19],"unless":[20],"ciphertext":[21],"is":[22,106],"maintained":[23],"the":[25,39,66,84,119,147],"memory":[26],"array":[27],"itself.":[28],"This":[29],"paper":[30],"presents":[31],"BipBipCache,":[32],"a":[33,55,73,80],"direct-mapped":[34],"cache":[35,47,85],"controller":[36],"integrates":[38],"BipBip":[40,70,149],"tweakable":[41],"block":[42],"cipher":[43],"(TBC)":[44],"to":[45],"encrypt":[46],"tags":[50],"real":[52],"time":[53],"using":[54],"C$^3$-style":[56],"24+40":[57],"bit":[58],"decomposition":[59],"of":[60,92,165,170],"each":[61],"64-bit":[62],"word.":[63],"We":[64,140],"reconstruct":[65],"first":[67,120],"pipelined":[68],"hardware":[69],"encryptor":[71,122,142],"from":[72],"decryptor-centric":[74],"specification":[75],"coordinate":[77],"it":[78],"with":[79,125],"3-cycle":[81,134],"decryptor":[82,144],"inside":[83],"datapath.":[86],"Our":[87],"threat":[88],"model":[89],"targets":[90],"confidentiality":[91],"cache-resident":[93],"contents":[94],"against":[95,146],"cold-boot,":[96],"bus,":[97],"readout":[100],"attacks.":[101],"A":[102],"key":[103],"architectural":[104],"result":[105],"6-cycle":[108,116],"encryption":[109],"latency":[110],"does":[111],"not":[112],"fully":[113],"translate":[114],"into":[115],"write":[117,135],"penalty:":[118],"three":[121],"stages":[123],"overlap":[124],"tag":[126],"decryption":[127],"hit":[129,138],"detection,":[130],"leaving":[131],"an":[132],"effective":[133],"commitment":[136],"verification.":[139],"verify":[141],"correctness":[145],"official":[148],"C++":[150],"reference":[151],"(five":[152],"vectors":[153],"each),":[154],"report":[155],"FPGA":[156],"resource":[157],"utilization":[158],"on":[159,176],"Xilinx":[160],"Artix-7":[161],"(3,356":[162],"LUTs,":[163],"16.1%":[164],"device;":[166],"crypto":[167],"logic":[168],"~79%":[169],"LUTs),":[171],"confirm":[173],"end-to-end":[174],"operation":[175],"hardware.":[177]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-06-25T00:00:00"}