{"id":"https://openalex.org/W7165619183","doi":"https://doi.org/10.48550/arxiv.2606.21454","title":"COMPOSE: Static Timing-driven Composable Reconfigurable Architecture for Accelerating Recurrence-Bound Loops","display_name":"COMPOSE: Static Timing-driven Composable Reconfigurable Architecture for Accelerating Recurrence-Bound Loops","publication_year":2026,"publication_date":"2026-06-19","ids":{"openalex":"https://openalex.org/W7165619183","doi":"https://doi.org/10.48550/arxiv.2606.21454"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.21454","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.21454","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.21454","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066607195","display_name":"Rohan Juneja","orcid":"https://orcid.org/0000-0002-6015-1084"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Juneja, Rohan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010709272","display_name":"Vishruti Ranjan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ranjan, Vishruti","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5099842155","display_name":"Rakshith Harish","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Harish, Rakshith","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5057413185","display_name":"Li-Shiuan Peh","orcid":"https://orcid.org/0000-0001-9010-6519"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peh, Li-Shiuan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7020000219345093,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7020000219345093,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.25279998779296875,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.017500000074505806,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.680899977684021},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6747000217437744},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5701000094413757},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.5516999959945679},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5167999863624573},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.47099998593330383},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.46880000829696655},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4372999966144562},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4178999960422516}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8149999976158142},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.680899977684021},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6747000217437744},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5701000094413757},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5699999928474426},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.5516999959945679},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5167999863624573},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.47099998593330383},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46880000829696655},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44530001282691956},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4372999966144562},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4178999960422516},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.39089998602867126},{"id":"https://openalex.org/C1306188","wikidata":"https://www.wikidata.org/wiki/Q4060687","display_name":"Nested loop join","level":2,"score":0.3894999921321869},{"id":"https://openalex.org/C2776834041","wikidata":"https://www.wikidata.org/wiki/Q25346349","display_name":"Execution model","level":2,"score":0.3741999864578247},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.3621000051498413},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.35760000348091125},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.3452000021934509},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3303000032901764},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.32899999618530273},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3264999985694885},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.3260999917984009},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.3206000030040741},{"id":"https://openalex.org/C19012869","wikidata":"https://www.wikidata.org/wiki/Q578372","display_name":"Response time","level":2,"score":0.30730000138282776},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.3066999912261963},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2863999903202057},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.2775000035762787},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.26829999685287476},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.26809999346733093},{"id":"https://openalex.org/C200130814","wikidata":"https://www.wikidata.org/wiki/Q362858","display_name":"Worst-case execution time","level":3,"score":0.2531000077724457},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.25029999017715454}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.21454","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.21454","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.21454","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.21454","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9180335998535156}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Coarse-Grained":[0],"Reconfigurable":[1],"Architectures":[2],"(CGRAs)":[3],"provide":[4],"a":[5,113,182],"spatially":[6,132],"programmable":[7],"substrate":[8],"well":[9],"suited":[10],"for":[11],"accelerating":[12],"compute-intensive":[13],"workloads":[14],"with":[15],"abundant":[16],"parallelism.":[17],"However,":[18],"traditional":[19],"CGRA":[20,115],"execution":[21,58,153],"models":[22],"rely":[23],"on":[24,85,188],"rigid,":[25],"fixed-size":[26],"processing":[27],"elements":[28],"(PEs)":[29],"that":[30,95,117,146],"are":[31],"statically":[32],"bound":[33],"to":[34,41,62,70],"individual":[35],"operations,":[36,68],"which":[37,175],"forces":[38],"inter-iteration":[39,144],"dependencies":[40,145],"be":[42],"resolved":[43],"through":[44],"serialized":[45],"scheduling.":[46],"This":[47],"limits":[48],"throughput":[49,148],"and":[50,73,88,138,149,194,204],"reduces":[51,161],"parallelism":[52],"across":[53,135],"loop":[54,136],"iterations.":[55],"Moreover,":[56],"static":[57,128],"schedules":[59],"often":[60],"fail":[61],"exploit":[63],"available":[64],"timing":[65,129],"slack":[66,156],"between":[67],"leading":[69],"resource":[71],"underutilization":[72],"increased":[74],"latency.":[75],"The":[76],"frequent":[77],"registering":[78],"of":[79,121,185],"intermediate":[80,170],"results":[81],"further":[82],"exacerbates":[83],"pressure":[84,164],"register":[86,162],"files":[87],"local":[89],"memories,":[90],"introducing":[91],"data":[92],"movement":[93],"overheads":[94],"reduce":[96],"energy":[97],"efficiency,":[98],"particularly":[99],"in":[100],"power":[101,205],"or":[102],"memory":[103,179],"constrained":[104],"environments.":[105],"To":[106],"address":[107],"these":[108],"challenges,":[109],"we":[110],"introduce":[111],"COMPOSE,":[112],"composable":[114],"architecture":[116,160],"enables":[118,150],"dynamic":[119],"formation":[120],"PEs":[122],"at":[123,201],"compile":[124],"time":[125],"guided":[126],"by":[127,154,165],"information.":[130],"By":[131],"fusing":[133],"operations":[134],"iterations":[137],"selectively":[139],"utilizing":[140],"slack,":[141],"COMPOSE":[142,187],"resolves":[143],"limit":[147],"low":[151],"latency":[152],"reducing":[155],"wastage.":[157],"Additionally,":[158],"the":[159],"file":[163],"deferring":[166],"output":[167],"registration":[168],"when":[169],"values":[171],"remain":[172],"locally":[173],"consumable,":[174],"significantly":[176],"lowers":[177],"redundant":[178],"traffic.":[180],"Across":[181],"diverse":[183],"set":[184],"workloads,":[186],"average":[189],"delivers":[190],"1.6x":[191],"performance":[192],"improvement":[193],"2.9x":[195],"EDP":[196],"reduction":[197],"over":[198],"state-of-the-art":[199],"(SOTA),":[200],"minimal":[202],"area":[203],"overheads.":[206]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-06-24T00:00:00"}