{"id":"https://openalex.org/W7164840145","doi":"https://doi.org/10.48550/arxiv.2606.13844","title":"Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems","display_name":"Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems","publication_year":2026,"publication_date":"2026-06-11","ids":{"openalex":"https://openalex.org/W7164840145","doi":"https://doi.org/10.48550/arxiv.2606.13844"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.13844","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.13844","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.13844","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070892312","display_name":"Haocong Luo","orcid":"https://orcid.org/0009-0009-0849-8724"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Luo, Haocong","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138643151","display_name":"F. Nisa Bostanci","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bostanc\u0131, F. Nisa","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056716458","display_name":"Ataberk Olgun","orcid":"https://orcid.org/0000-0001-5333-5726"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Olgun, Ataberk","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120244612","display_name":"Maria Makeenkova","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Makeenkova, Maria","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088427036","display_name":"Ziad Malik","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Malik, Ziad","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5117932436","display_name":"Ipek Akdeniz","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Akdeniz, Ipek","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5138689159","display_name":"Onur Mutlu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mutlu, Onur","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8794999718666077,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8794999718666077,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.04230000078678131,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.021700000390410423,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8427000045776367},{"id":"https://openalex.org/keywords/usability","display_name":"Usability","score":0.6571999788284302},{"id":"https://openalex.org/keywords/python","display_name":"Python (programming language)","score":0.5501999855041504},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.5483999848365784},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.44429999589920044},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.42829999327659607},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.376800000667572},{"id":"https://openalex.org/keywords/user-interface","display_name":"User interface","score":0.3434000015258789}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8427000045776367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7504000067710876},{"id":"https://openalex.org/C170130773","wikidata":"https://www.wikidata.org/wiki/Q216378","display_name":"Usability","level":2,"score":0.6571999788284302},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5623999834060669},{"id":"https://openalex.org/C519991488","wikidata":"https://www.wikidata.org/wiki/Q28865","display_name":"Python (programming language)","level":2,"score":0.5501999855041504},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.5483999848365784},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4668999910354614},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.44429999589920044},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.42829999327659607},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.376800000667572},{"id":"https://openalex.org/C89505385","wikidata":"https://www.wikidata.org/wiki/Q47146","display_name":"User interface","level":2,"score":0.3434000015258789},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3393000066280365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.29350000619888306},{"id":"https://openalex.org/C156731835","wikidata":"https://www.wikidata.org/wiki/Q751740","display_name":"Memory leak","level":4,"score":0.28529998660087585},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.2851000130176544},{"id":"https://openalex.org/C37789001","wikidata":"https://www.wikidata.org/wiki/Q782543","display_name":"Graphical user interface","level":2,"score":0.28110000491142273},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2793000042438507},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.27799999713897705},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.275299996137619},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.2721000015735626},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.26589998602867126},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2639000117778778},{"id":"https://openalex.org/C20574231","wikidata":"https://www.wikidata.org/wiki/Q844605","display_name":"Backward compatibility","level":2,"score":0.2630999982357025}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.13844","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.13844","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.13844","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.13844","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.646530032157898}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Ramulator":[0,7,43,69,130,168,180],"2.1":[1,44,70,131,169,181],"is":[2,182],"a":[3,72,80,133],"major":[4],"overhaul":[5],"of":[6,19,32,106,117,145],"2.0":[8],"that":[9,84,139],"substantially":[10],"improves":[11],"the":[12,33,107],"simulator":[13],"in":[14,50,95,127],"three":[15],"directions:":[16],"1)":[17,85,142],"support":[18,46],"modern":[20],"and":[21,24,30,35,40,52,56,62,67,75,97,120,136,150,154,166,174,186],"emerging":[22,53],"DRAM":[23,54,92,118,147,176],"memory-controller":[25,151],"features,":[26],"2)":[27,98,155],"better":[28],"usability":[29,66],"extensibility":[31],"simulator,":[34],"3)":[36],"more":[37],"comprehensive":[38,134],"tests":[39],"validation":[41,137,144],"workflows.":[42,123],"adds":[45],"for":[47,103],"advanced":[48],"features":[49],"recent":[51],"standards":[55,119],"memory":[57],"controllers,":[58],"including":[59],"HBM3/4,":[60],"LPDDR5/6,":[61],"GDDR7.":[63],"To":[64,124,162],"improve":[65,125],"extensibility,":[68],"introduces":[71],"Python-based":[73],"modeling":[74],"configuration":[76],"interface":[77],"backed":[78],"by":[79],"two-way":[81],"code-generation":[82],"framework":[83],"hides":[86],"low-level":[87],"C++":[88],"code":[89],"behind":[90],"high-level":[91],"specifications":[93],"written":[94],"Python,":[96],"automatically":[99],"creates":[100],"Python":[101],"proxies":[102],"all":[104],"components":[105],"simulator.":[108],"Doing":[109],"so":[110],"enables":[111],"users":[112],"to":[113],"rapidly":[114],"create":[115],"variants":[116],"automate":[121],"design-space-exploration":[122],"trustworthiness":[126],"simulation":[128],"results,":[129],"provides":[132],"testing":[135],"infrastructure":[138],"covers":[140],"both":[141],"fine-grained":[143],"specific":[146],"timing":[148],"constraints":[149],"scheduling":[152],"behavior,":[153],"system-level":[156],"performance":[157,164],"evaluation":[158],"using":[159],"latency-throughput":[160],"curves.":[161],"aid":[163],"analysis":[165],"debugging,":[167],"also":[170],"includes":[171],"an":[172],"easy-to-use":[173],"high-performance":[175],"command":[177],"trace":[178],"visualizer.":[179],"open-source":[183],"on":[184],"GitHub":[185],"under":[187],"active":[188],"development.":[189]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-06-16T00:00:00"}