{"id":"https://openalex.org/W7164183489","doi":"https://doi.org/10.48550/arxiv.2606.11065","title":"Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices","display_name":"Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices","publication_year":2026,"publication_date":"2026-06-09","ids":{"openalex":"https://openalex.org/W7164183489","doi":"https://doi.org/10.48550/arxiv.2606.11065"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.11065","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.11065","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.11065","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092096811","display_name":"Titus Borntr\u00e4ger","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Borntr\u00e4ger, Titus","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138374079","display_name":"Shane Fleming","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fleming, Shane","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002208253","display_name":"Philipp Holzinger","orcid":"https://orcid.org/0000-0002-2912-0650"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Holzinger, Philipp","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030918623","display_name":"Dietmar Fey","orcid":"https://orcid.org/0000-0002-6077-4732"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fey, Dietmar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031107943","display_name":"Michaela Blott","orcid":"https://orcid.org/0000-0002-7833-4057"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Blott, Michaela","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5055093027","display_name":"Thomas B. Preu\u00dfer","orcid":"https://orcid.org/0000-0003-3998-7896"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Preu\u00dfer, Thomas B.","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.45080000162124634,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.45080000162124634,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.17870000004768372,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.07859999686479568,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6901999711990356},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6884999871253967},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6833999752998352},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6373000144958496},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.538100004196167},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4499000012874603},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.3767000138759613},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.3580999970436096},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.349700003862381}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7682999968528748},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6901999711990356},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6884999871253967},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6833999752998352},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6373000144958496},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.538100004196167},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4499000012874603},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43050000071525574},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3871999979019165},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3785000145435333},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.3767000138759613},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37279999256134033},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3580999970436096},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.349700003862381},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.33649998903274536},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.3343999981880188},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3172000050544739},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.31380000710487366},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.3012000024318695},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2994999885559082},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.2953999936580658},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2935999929904938},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.2903999984264374},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.28870001435279846},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.2806999981403351},{"id":"https://openalex.org/C2984842247","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep neural networks","level":3,"score":0.25929999351501465},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.2540999948978424}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.11065","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.11065","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.11065","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.11065","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Deep":[0],"Neural":[1],"Networks":[2],"increasingly":[3],"employ":[4],"low-precision":[5],"quantization":[6],"to":[7,74,83,150],"reduce":[8,133],"computational":[9],"requirements.":[10],"While":[11,39],"FPGAs":[12],"are":[13,33,64,123],"well":[14],"suited":[15],"for":[16,113,119,145],"workloads":[17],"with":[18,89],"heterogeneous":[19],"precisions,":[20],"their":[21],"dedicated":[22],"digital":[23],"signal":[24],"processing":[25],"(DSP)":[26],"slices":[27],"only":[28,58],"feature":[29],"fixed-width":[30],"datapaths":[31],"that":[32],"significantly":[34],"underutilized":[35],"by":[36,97,137,143],"low-bitwidth":[37],"arithmetic.":[38],"previous":[40],"approaches":[41],"have":[42],"already":[43],"introduced":[44],"the":[45,51,67,75,99,117,134,141,146,151],"packing":[46],"of":[47,69],"multiple":[48,86],"values":[49],"onto":[50],"same":[52],"wide":[53,94],"DSP":[54],"datapath,":[55],"they":[56],"either":[57],"support":[59,71],"specific":[60],"fixed":[61],"bitwidths":[62,91],"or":[63],"wasteful":[65],"regarding":[66],"use":[68],"additional":[70],"logic":[72],"external":[73],"DSP.":[76],"This":[77],"paper":[78],"proposes":[79],"an":[80],"efficient":[81],"method":[82],"dynamically":[84],"pack":[85],"(un-)signed":[87],"inputs":[88],"arbitrary":[90],"into":[92,125],"a":[93],"multiplier":[95],"path":[96],"leveraging":[98],"DSP's":[100],"internal":[101],"pre-adder.":[102],"Building":[103],"on":[104],"this,":[105],"we":[106,132],"present":[107],"two":[108],"distinct":[109],"architectures,":[110],"one":[111],"optimized":[112],"matrix-vector":[114],"multiplications":[115],"and":[116,139],"other":[118],"convolutions.":[120],"Our":[121],"implementations":[122],"integrated":[124],"AMD's":[126],"FINN":[127,152],"framework.":[128],"With":[129],"these":[130],"optimizations,":[131],"LUT":[135],"utilization":[136],"21%":[138],"increase":[140],"FPS/DSP":[142],"36%":[144],"UltraNet":[147],"model":[148],"compared":[149],"reference.":[153]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-06-11T00:00:00"}