{"id":"https://openalex.org/W7164005276","doi":"https://doi.org/10.48550/arxiv.2606.08430","title":"Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory","display_name":"Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory","publication_year":2026,"publication_date":"2026-06-07","ids":{"openalex":"https://openalex.org/W7164005276","doi":"https://doi.org/10.48550/arxiv.2606.08430"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.08430","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.08430","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.08430","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5138285905","display_name":"Yiqi Zhou","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhou, Yiqi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138226067","display_name":"Junhao Lu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lu, Junhao","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138206716","display_name":"Jiale Yu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yu, Jiale","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138282230","display_name":"Zhuo Xu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xu, Zhuo","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138281517","display_name":"Yang He","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"He, Yang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138242338","display_name":"Yue Yuan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yuan, Yue","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138244564","display_name":"Shan SHEN","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shen, Shan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5138259281","display_name":"Daying Sun","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sun, Daying","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5918999910354614,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5918999910354614,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.2587999999523163,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.025499999523162842,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8296999931335449},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.450300008058548},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41769999265670776},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.40070000290870667},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.384799987077713},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3596999943256378},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.34380000829696655},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.320499986410141}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8296999931335449},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5569000244140625},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.450300008058548},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.446399986743927},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41769999265670776},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.40070000290870667},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.384799987077713},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38280001282691956},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3596999943256378},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.34380000829696655},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.320499986410141},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.30720001459121704},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30559998750686646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29649999737739563},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.29280000925064087},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2915000021457672},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.28929999470710754},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2825999855995178},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2718999981880188},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.26660001277923584}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.08430","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.08430","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.08430","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.08430","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8771512508392334}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Digital":[0],"Compute-in-Memory":[1],"(DCiM)":[2],"reduces":[3],"data":[4],"movement":[5],"and":[6,28,34,54,86,111,127,150],"has":[7],"become":[8],"a":[9,84,87,144],"promising":[10],"solution":[11],"for":[12,32,73,147],"energy-efficient":[13],"edge":[14],"AI.":[15],"However,":[16],"most":[17],"existing":[18],"DCiM":[19,48,156],"frameworks":[20],"still":[21],"primarily":[22],"target":[23],"integer":[24],"or":[25],"fixed-point":[26],"arithmetic,":[27],"provide":[29],"limited":[30],"support":[31,153],"compiler-integrated":[33,139],"accuracy-configurable":[35,65],"floating-point":[36,43,66,117,141,152],"computation.":[37],"Directly":[38],"integrating":[39],"conventional":[40],"IEEE":[41],"754":[42],"units":[44],"into":[45,69],"dense":[46],"SRAM-based":[47,74,155],"arrays,":[49],"however,":[50],"incurs":[51],"high":[52],"area":[53,109],"power":[55,113],"overhead.":[56,121],"To":[57],"address":[58],"this":[59,61],"challenge,":[60],"work":[62],"presents":[63],"an":[64],"multiplier":[67,79,90],"integrated":[68],"the":[70],"OpenACM":[71],"framework":[72],"DCiM.":[75],"An":[76],"exact":[77,116],"IEEE~754-compliant":[78],"is":[80,91,143,161],"first":[81],"implemented":[82],"as":[83],"baseline,":[85],"mantissa-segmentation-based":[88],"approximate":[89,140],"then":[92],"proposed":[93],"to":[94,106],"reduce":[95],"hardware":[96],"cost":[97],"while":[98],"preserving":[99],"numerical":[100],"fidelity.":[101],"Post-layout":[102],"results":[103,136],"show":[104],"up":[105],"69%":[107],"logic":[108],"reduction":[110],"72%":[112],"savings":[114],"over":[115],"designs":[118],"without":[119],"delay":[120],"Evaluations":[122],"on":[123,163],"image":[124],"processing":[125],"tasks":[126],"ResNet-18":[128],"inference":[129],"further":[130],"demonstrate":[131],"negligible":[132],"accuracy":[133],"degradation.":[134],"These":[135],"indicate":[137],"that":[138],"multiplication":[142],"practical":[145],"approach":[146],"enabling":[148],"efficient":[149],"configurable":[151],"in":[154],"systems.":[157],"The":[158],"Floating-Point":[159],"Multiplier":[160],"available":[162],"https://github.com/ShenShan123/OpenACM":[164]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-06-10T00:00:00"}
