{"id":"https://openalex.org/W7163905057","doi":"https://doi.org/10.48550/arxiv.2606.06530","title":"RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits","display_name":"RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits","publication_year":2026,"publication_date":"2026-06-03","ids":{"openalex":"https://openalex.org/W7163905057","doi":"https://doi.org/10.48550/arxiv.2606.06530"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2606.06530","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.06530","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2606.06530","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5128709719","display_name":"Felix Arnold","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arnold, Felix","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120016987","display_name":"Ryan Amaudruz","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Amaudruz, Ryan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138177910","display_name":"Dimitrios Tsaras","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tsaras, Dimitrios","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050957615","display_name":"Renzo Andri","orcid":"https://orcid.org/0000-0002-8776-5158"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andri, Renzo","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5138152093","display_name":"Lukas Cavigelli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Cavigelli, Lukas","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7930999994277954,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7930999994277954,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.058400001376867294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.04340000078082085,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.527899980545044},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4894999861717224},{"id":"https://openalex.org/keywords/multi-objective-optimization","display_name":"Multi-objective optimization","score":0.45080000162124634},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4325000047683716},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.42179998755455017},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3982999920845032},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.38199999928474426},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.37549999356269836},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.36489999294281006},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.3425000011920929}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6715999841690063},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.527899980545044},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4894999861717224},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.46480000019073486},{"id":"https://openalex.org/C68781425","wikidata":"https://www.wikidata.org/wiki/Q2052203","display_name":"Multi-objective optimization","level":2,"score":0.45080000162124634},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4325000047683716},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.42179998755455017},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4117000102996826},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4018000066280365},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3982999920845032},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3901999890804291},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.38199999928474426},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.37549999356269836},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.36489999294281006},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3425000011920929},{"id":"https://openalex.org/C139571649","wikidata":"https://www.wikidata.org/wiki/Q1156793","display_name":"Program optimization","level":3,"score":0.3248000144958496},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3158000111579895},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3122999966144562},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.3059999942779541},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.30169999599456787},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2987000048160553},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2946000099182129},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.2833999991416931},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.28290000557899475},{"id":"https://openalex.org/C2777466363","wikidata":"https://www.wikidata.org/wiki/Q17008971","display_name":"Design tool","level":2,"score":0.2775000035762787},{"id":"https://openalex.org/C18555067","wikidata":"https://www.wikidata.org/wiki/Q8375051","display_name":"Joint (building)","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.2727000117301941},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.27070000767707825},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.26930001378059387},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.26829999685287476},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.26570001244544983},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26249998807907104},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.2551000118255615},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.2533999979496002},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.2524999976158142}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2606.06530","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.06530","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2606.06530","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2606.06530","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[{"score":0.5334226489067078,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"We":[0,44],"present":[1],"RTLScout,":[2],"an":[3,78,85],"autonomous":[4],"system":[5],"that":[6],"combines":[7],"LLM-driven":[8],"agentic":[9,68,71],"design":[10,106,145],"with":[11,90],"circuit-level":[12],"synthesis":[13],"optimization":[14,119],"and":[15,25,42,55,77,98,116],"arithmetic":[16,74],"architecture":[17,75],"sweeps.":[18],"An":[19],"LLM":[20],"agent":[21,60],"iteratively":[22],"writes,":[23],"evaluates,":[24],"refines":[26],"RTL":[27],"designs":[28,54,129],"using":[29],"tool":[30],"calls,":[31],"guided":[32],"by":[33,96,100],"quantitative":[34],"PPA":[35],"(power,":[36],"performance,":[37],"area)":[38],"feedback":[39],"from":[40],"Yosys":[41],"OpenROAD.":[43],"introduce":[45],"a":[46,104,124,132,142],"multi-run":[47],"elite":[48],"pool":[49],"framework,":[50],"where":[51],"the":[52,147],"best":[53],"lessons":[56],"learned":[57],"seed":[58],"subsequent":[59],"runs.":[61],"The":[62,137],"pipeline":[63],"comprises":[64],"four":[65],"complementary":[66],"phases:":[67],"code":[69],"optimization,":[70],"gate-level":[72,81,118],"rewriting,":[73],"sweeps,":[76],"optional":[79],"high-effort":[80,117],"refinement":[82,125],"pass.":[83],"On":[84],"IEEE-754-compliant":[86],"16-bit":[87],"floating-point":[88],"multiplier":[89],"subnormal":[91],"support,":[92],"RTLScout":[93],"reduces":[94],"area":[95],"35%":[97],"delay":[99],"45%":[101],"relative":[102],"to":[103],"starting":[105],"synthesized":[107],"in":[108],"ASAP7":[109],"technology.":[110,149],"Each":[111],"phase":[112],"provides":[113],"distinct":[114],"improvements,":[115],"is":[120],"most":[121],"effective":[122],"as":[123],"of":[126],"already":[127],"well-optimized":[128],"rather":[130],"than":[131],"substitute":[133],"for":[134],"earlier":[135],"stages.":[136],"resulting":[138],"Pareto":[139],"front":[140],"outperforms":[141],"commercial-tool":[143],"reference":[144],"on":[146],"same":[148]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-06-09T00:00:00"}
