{"id":"https://openalex.org/W7160874444","doi":"https://doi.org/10.48550/arxiv.2605.07782","title":"CktFormalizer: Autoformalization of Natural Language into Circuit Representations","display_name":"CktFormalizer: Autoformalization of Natural Language into Circuit Representations","publication_year":2026,"publication_date":"2026-05-08","ids":{"openalex":"https://openalex.org/W7160874444","doi":"https://doi.org/10.48550/arxiv.2605.07782"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2605.07782","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.07782","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2605.07782","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5135896149","display_name":"Jing Xiong","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiong, Jing","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5135862795","display_name":"Qi Han","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Han, Qi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125260117","display_name":"Chenchen Ding","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ding, Chenchen","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100432152","display_name":"Xiao He","orcid":"https://orcid.org/0000-0002-2306-0642"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiao, He","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122136707","display_name":"Zunhai Su","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Su, Zunhai","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5135846828","display_name":"Chaofan Tao","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tao, Chaofan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5072120057","display_name":"Ngai Wong","orcid":"https://orcid.org/0000-0002-3026-0108"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wong, Ngai","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5667999982833862,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5667999982833862,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.3310000002384186,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.01600000075995922,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7829999923706055},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6489999890327454},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.5573999881744385},{"id":"https://openalex.org/keywords/mathematical-proof","display_name":"Mathematical proof","score":0.5483999848365784},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.510200023651123},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5023999810218811},{"id":"https://openalex.org/keywords/propositional-formula","display_name":"Propositional formula","score":0.45719999074935913},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4496999979019165},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.43529999256134033}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7829999923706055},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7129999995231628},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6489999890327454},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.5573999881744385},{"id":"https://openalex.org/C108710211","wikidata":"https://www.wikidata.org/wiki/Q11538","display_name":"Mathematical proof","level":2,"score":0.5483999848365784},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5245000123977661},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.510200023651123},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5023999810218811},{"id":"https://openalex.org/C74640108","wikidata":"https://www.wikidata.org/wiki/Q1372900","display_name":"Propositional formula","level":5,"score":0.45719999074935913},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4496999979019165},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.43529999256134033},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3804999887943268},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.376800000667572},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.3456999957561493},{"id":"https://openalex.org/C62073222","wikidata":"https://www.wikidata.org/wiki/Q1572108","display_name":"Natural deduction","level":2,"score":0.3375000059604645},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.326200008392334},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.32589998841285706},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3228999972343445},{"id":"https://openalex.org/C114408938","wikidata":"https://www.wikidata.org/wiki/Q333373","display_name":"Abstract syntax","level":3,"score":0.3190999925136566},{"id":"https://openalex.org/C195324797","wikidata":"https://www.wikidata.org/wiki/Q33742","display_name":"Natural language","level":2,"score":0.30410000681877136},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2955000102519989},{"id":"https://openalex.org/C66746571","wikidata":"https://www.wikidata.org/wiki/Q1134833","display_name":"ENCODE","level":3,"score":0.2766999900341034},{"id":"https://openalex.org/C203265346","wikidata":"https://www.wikidata.org/wiki/Q11387554","display_name":"Proof assistant","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C60048249","wikidata":"https://www.wikidata.org/wiki/Q37437","display_name":"Syntax","level":2,"score":0.26969999074935913},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.2678000032901764},{"id":"https://openalex.org/C70846408","wikidata":"https://www.wikidata.org/wiki/Q220433","display_name":"Logical equivalence","level":3,"score":0.2563999891281128},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.2547999918460846},{"id":"https://openalex.org/C196836630","wikidata":"https://www.wikidata.org/wiki/Q4753279","display_name":"And-inverter graph","level":4,"score":0.2535000145435333},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2526000142097473},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.2517000138759613}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2605.07782","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.07782","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2605.07782","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.07782","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"LLMs":[0],"can":[1],"generate":[2],"hardware":[3,41,67],"descriptions":[4],"from":[5],"natural":[6],"language":[7],"specifications,":[8],"but":[9],"the":[10,122,160],"resulting":[11],"Verilog":[12,147],"often":[13],"contains":[14],"width":[15],"mismatches,":[16],"combinational":[17],"loops,":[18],"and":[19,64,99,118,135,165,179],"incomplete":[20],"case":[21,62],"logic":[22],"that":[23,38,72,85,192],"pass":[24,142],"syntax":[25],"checks":[26],"yet":[27],"fail":[28],"in":[29,48],"synthesis":[30,98],"or":[31],"silicon.":[32],"We":[33],"present":[34],"CktFormalizer,":[35],"a":[36,44],"framework":[37],"redirects":[39],"LLM-driven":[40],"generation":[42,148],"through":[43,183],"dependently-typed":[45],"HDL":[46],"embedded":[47],"Lean":[49,51],"4.":[50],"serves":[52],"three":[53],"roles:":[54],"(i)":[55],"type":[56],"checker:dependent":[57],"types":[58],"encode":[59],"bit-width":[60],"constraints,":[61],"coverage,":[63],"acyclicity,":[65],"turning":[66],"defects":[68,84],"into":[69],"compile-time":[70],"errors":[71],"guide":[73],"iterative":[74],"repair;":[75],"(ii)":[76],"correctness":[77],"firewall:compiled":[78],"designs":[79,96,158],"are":[80],"structurally":[81],"free":[82],"of":[83,94,104,124,156],"cause":[86],"silent":[87],"backend":[88,153],"failures":[89],"(the":[90],"baseline":[91],"loses":[92],"20%":[93],"correct":[95],"during":[97],"routing;":[100],"CktFormalizer":[101,139],"preserves":[102],"all":[103],"them);":[105],"(iii)":[106],"proof":[107,190],"assistant:the":[108],"agent":[109],"constructs":[110],"machine-checked":[111],"equivalence":[112],"proofs":[113],"over":[114],"arbitrary":[115],"input":[116],"sequences":[117],"parameterized":[119],"widths,":[120],"beyond":[121],"reach":[123],"bounded":[125],"SMT-based":[126],"checking.":[127],"On":[128],"VerilogEval":[129],"(156":[130],"problems),":[131,134,138],"RTLLM":[132],"(50":[133],"ResBench":[136],"(56":[137],"achieves":[140],"simulation":[141],"rates":[143],"competitive":[144],"with":[145,187],"direct":[146],"while":[149],"delivering":[150],"substantially":[151],"higher":[152],"realizability:":[154],"95--100%":[155],"compiled":[157],"complete":[159],"full":[161],"synthesis,":[162],"place-and-route,":[163],"DRC,":[164],"LVS":[166],"flow.":[167],"A":[168],"closed-loop":[169],"PPA":[170],"optimization":[171],"stage":[172],"yields":[173],"up":[174],"to":[175,199],"35%":[176],"area":[177],"reduction":[178,182],"30%":[180],"power":[181],"validated":[184],"architecture":[185],"exploration,":[186],"automated":[188],"theorem":[189],"ensuring":[191],"each":[193],"optimized":[194],"variant":[195],"remains":[196],"functionally":[197],"equivalent":[198],"its":[200],"formal":[201],"specification.":[202]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-05-12T00:00:00"}
