{"id":"https://openalex.org/W7160500043","doi":"https://doi.org/10.48550/arxiv.2605.04178","title":"Microbenchmark-Driven Analytical Performance Modeling Across Modern GPU Architectures","display_name":"Microbenchmark-Driven Analytical Performance Modeling Across Modern GPU Architectures","publication_year":2026,"publication_date":"2026-05-05","ids":{"openalex":"https://openalex.org/W7160500043","doi":"https://doi.org/10.48550/arxiv.2605.04178"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2605.04178","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.04178","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2605.04178","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047370789","display_name":"Aaron Jarmusch","orcid":"https://orcid.org/0000-0002-5532-6513"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jarmusch, Aaron","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5135555813","display_name":"Sunita Chandrasekaran","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chandrasekaran, Sunita","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8533999919891357,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8533999919891357,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.05469999834895134,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.016100000590085983,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tensor","display_name":"Tensor (intrinsic definition)","score":0.5730000138282776},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5080999732017517},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.48669999837875366},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.37549999356269836},{"id":"https://openalex.org/keywords/matrix","display_name":"Matrix (chemical analysis)","score":0.31940001249313354},{"id":"https://openalex.org/keywords/data-modeling","display_name":"Data modeling","score":0.3172000050544739},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.29919999837875366}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7591999769210815},{"id":"https://openalex.org/C155281189","wikidata":"https://www.wikidata.org/wiki/Q3518150","display_name":"Tensor (intrinsic definition)","level":2,"score":0.5730000138282776},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5267000198364258},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5080999732017517},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.48669999837875366},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38929998874664307},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.37549999356269836},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3677999973297119},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.34459999203681946},{"id":"https://openalex.org/C106487976","wikidata":"https://www.wikidata.org/wiki/Q685816","display_name":"Matrix (chemical analysis)","level":2,"score":0.31940001249313354},{"id":"https://openalex.org/C67186912","wikidata":"https://www.wikidata.org/wiki/Q367664","display_name":"Data modeling","level":2,"score":0.3172000050544739},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.29919999837875366},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.2989000082015991},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2969000041484833},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.29580000042915344},{"id":"https://openalex.org/C45237549","wikidata":"https://www.wikidata.org/wiki/Q1376796","display_name":"Restructuring","level":2,"score":0.2856999933719635},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.28290000557899475},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.2554999887943268},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.25029999017715454}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2605.04178","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.04178","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2605.04178","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2605.04178","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Rapidly":[0],"evolving":[1],"GPU":[2],"architectures":[3],"featuring":[4],"complex":[5],"memory":[6],"hierarchies,":[7],"matrix":[8],"units,":[9],"and":[10,22,27,36,57,71,81,105,116,119,124,138],"varied":[11],"precision":[12],"formats":[13],"continue":[14],"to":[15,121],"widen":[16],"the":[17,47,63,95,101,132],"gap":[18],"between":[19],"theoretical":[20],"peaks":[21],"achievable":[23],"performance.":[24],"We":[25,98],"design":[26],"develop":[28],"analytical":[29],"performance":[30],"models":[31,102,109,133,137],"for":[32,61],"NVIDIA":[33],"Blackwell":[34],"(B200)":[35],"AMD":[37],"CDNA3":[38],"(MI300A)":[39],"grounded":[40],"in":[41],"systematic":[42],"microbenchmark":[43],"characterization.":[44],"For":[45],"Blackwell,":[46],"model":[48,64],"captures":[49,65],"Tensor":[50],"Memory":[51],"(TMEM),":[52],"asynchronous":[53],"bulk":[54],"copy":[55],"(TMA),":[56],"5th-generation":[58],"tensor":[59],"cores;":[60],"CDNA3,":[62],"Infinity":[66],"Cache":[67],"hierarchy,":[68],"VGPR":[69],"constraints,":[70],"occupancy.":[72],"Validation":[73],"yields":[74],"1.31%":[75],"MAE":[76],"on":[77,83,94],"B200":[78],"(21":[79],"kernels)":[80],"0.09%":[82],"MI300A":[84],"(27":[85],"kernels),":[86],"while":[87],"naive":[88],"roofline":[89],"baselines":[90],"exceed":[91],"95%":[92],"error":[93],"same":[96],"kernels.":[97],"further":[99],"validate":[100],"using":[103],"Rodinia~3.1":[104],"SPEChpc":[106],"2021":[107],"Tiny.The":[108],"are":[110,134],"updated":[111],"with":[112],"HBM":[113],"bandwidth,":[114],"capacity,":[115],"cache":[117],"parameters":[118],"applied":[120],"H200":[122],"(Hopper)":[123],"MI250X":[125],"(CDNA2),":[126],"indicating":[127],"no":[128],"major":[129],"restructuring":[130],"of":[131],"needed.":[135],"All":[136],"benchmarks":[139],"will":[140],"be":[141],"released":[142],"as":[143],"open-source":[144],"upon":[145],"acceptance.":[146]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-05-08T00:00:00"}