{"id":"https://openalex.org/W7158625232","doi":"https://doi.org/10.48550/arxiv.2604.26821","title":"Exploring the Efficiency of 3D-Stacked AI Chip Architecture for LLM Inference with Voxel","display_name":"Exploring the Efficiency of 3D-Stacked AI Chip Architecture for LLM Inference with Voxel","publication_year":2026,"publication_date":"2026-04-29","ids":{"openalex":"https://openalex.org/W7158625232","doi":"https://doi.org/10.48550/arxiv.2604.26821"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2604.26821","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.26821","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2604.26821","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5134917451","display_name":"Yiqi Liu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liu, Yiqi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119897581","display_name":"Noelle Crawford","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Crawford, Noelle","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134883837","display_name":"Michael Wang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wang, Michael","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134887015","display_name":"Jilong Xue","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xue, Jilong","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5134878126","display_name":"Jian Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Huang, Jian","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.4925999939441681,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.4925999939441681,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.2955999970436096,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.06700000166893005,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.746399998664856},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6499000191688538},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4851999878883362},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.46160000562667847},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4196000099182129},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3828999996185303},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.35569998621940613},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.35100001096725464},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.32850000262260437}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8174999952316284},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.746399998664856},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6499000191688538},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5332000255584717},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4851999878883362},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.46160000562667847},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4196000099182129},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3961000144481659},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3828999996185303},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.35569998621940613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3522999882698059},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.35100001096725464},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3481999933719635},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.32850000262260437},{"id":"https://openalex.org/C157170001","wikidata":"https://www.wikidata.org/wiki/Q4781507","display_name":"Applications of artificial intelligence","level":2,"score":0.3280999958515167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32679998874664307},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.310699999332428},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.2937999963760376},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2937000095844269},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.29350000619888306},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.29030001163482666},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.2825999855995178},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2806999981403351},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.27549999952316284},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.2721000015735626},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.26660001277923584},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2558000087738037},{"id":"https://openalex.org/C54170458","wikidata":"https://www.wikidata.org/wiki/Q663554","display_name":"Voxel","level":2,"score":0.25110000371932983}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2604.26821","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.26821","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2604.26821","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.26821","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"To":[0],"overcome":[1],"the":[2,62,65,98,118,132,146,152,165,202,216,227,242,245,253,256],"well-known":[3],"memory":[4,36,41],"bottleneck":[5],"of":[6,64,120,154,169,172,205,219,255],"AI":[7,32,49,67,122,174,209,232,258],"chips,":[8,175],"3D":[9,207],"stacked":[10,208],"architectures":[11],"that":[12,84,140,201,247],"employ":[13],"advanced":[14],"packaging":[15],"technology":[16],"with":[17,156,244],"high-density":[18],"through-silicon":[19],"vias":[20],"(TSVs)":[21],"pins":[22],"have":[23],"proven":[24],"to":[25,60,70,78,90,97,115,144,231],"be":[26],"a":[27,52,108,137,206],"promising":[28],"solution.":[29],"The":[30],"3D-stacked":[31,66,121,173,257],"chip":[33,210,259],"enables":[34,131],"ultra-high":[35],"bandwidth":[37],"between":[38],"compute":[39,178],"and":[40,96,110,167,186,195,234,266],"by":[42,135,215],"stacking":[43],"numerous":[44],"DRAM":[45,189,235],"banks":[46],"atop":[47],"many":[48],"cores":[50],"in":[51],"distributed":[53,73],"manner.":[54],"However,":[55],"it":[56],"is":[57,213],"not":[58,211],"easy":[59],"explore":[61],"efficiency":[63,119,204],"chip,":[68],"due":[69],"its":[71],"unique":[72],"nature.":[74],"And":[75],"we":[76,105,162],"need":[77],"carefully":[79],"consider":[80],"multiple":[81],"intertwined":[82],"factors":[83],"range":[85],"from":[86,229],"upper-level":[87],"computing":[88],"paradigm":[89],"machine":[91],"learning":[92],"(ML)":[93],"compiler":[94],"optimizations,":[95],"underlying":[99],"hardware":[100],"architecture.":[101],"In":[102],"this":[103],"paper,":[104,243],"develop":[106],"Voxel,":[107],"fast":[109],"compiler-aware":[111],"end-to-end":[112,203],"simulation":[113],"framework":[114],"facilitate":[116],"exploring":[117],"chips":[123],"for":[124,270],"large":[125],"language":[126],"model":[127,147],"(LLM)":[128],"inference.":[129],"Voxel":[130,155,265],"software/hardware":[133],"co-exploration":[134],"employing":[136],"programming":[138],"interface":[139],"allows":[141],"ML":[142],"compilers":[143],"customize":[145],"execution":[148],"plans.":[149],"After":[150],"validating":[151],"results":[153,269],"an":[157],"emulator":[158],"on":[159,226,252],"real":[160],"silicon,":[161],"thoroughly":[163],"examine":[164],"impact":[166],"correlation":[168],"different":[170],"aspects":[171],"including":[176],"state-of-the-art":[177],"paradigms,":[179],"tile-to-core":[180],"mapping,":[181,183],"tensor-to-bank":[182],"NoC":[184],"topologies":[185],"link":[187],"bandwidth,":[188,191],"bank":[190],"per-core":[192],"SRAM":[193],"capacity,":[194],"energy/thermal":[196],"constraints.":[197],"Our":[198],"findings":[199,240],"disclose":[200],"only":[212],"determined":[214],"cooperative":[217],"function":[218],"these":[220],"factors,":[221],"but":[222],"also":[223],"significantly":[224],"depends":[225],"mappings":[228],"tiles":[230],"core":[233],"banks.":[236],"We":[237,261],"report":[238],"our":[239,267],"throughout":[241],"expectation":[246],"they":[248],"will":[249,262],"shed":[250],"light":[251],"development":[254],"ecosystem.":[260],"open":[263],"source":[264],"study":[268],"public":[271],"research.":[272]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-05-01T00:00:00"}