{"id":"https://openalex.org/W7155038346","doi":"https://doi.org/10.48550/arxiv.2604.18162","title":"VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation","display_name":"VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation","publication_year":2026,"publication_date":"2026-04-20","ids":{"openalex":"https://openalex.org/W7155038346","doi":"https://doi.org/10.48550/arxiv.2604.18162"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2604.18162","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.18162","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2604.18162","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5134099775","display_name":"Yan Tan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tan, Yan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134119096","display_name":"Tong Liu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liu, Tong","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101710992","display_name":"Xiangchen Meng","orcid":"https://orcid.org/0000-0002-2392-2740"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Meng, Xiangchen","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5014819244","display_name":"Yangdi Lyu","orcid":"https://orcid.org/0000-0001-8322-156X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lyu, Yangdi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","score":0.2831999957561493,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","score":0.2831999957561493,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10181","display_name":"Natural Language Processing Techniques","score":0.0835999995470047,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.0746999979019165,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6840999722480774},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.459199994802475},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4526999890804291},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4458000063896179},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4097999930381775},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3792000114917755},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.3287000060081482},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.3151000142097473}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.83160001039505},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6840999722480774},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5175999999046326},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.47679999470710754},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.459199994802475},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4526999890804291},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4458000063896179},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4097999930381775},{"id":"https://openalex.org/C204321447","wikidata":"https://www.wikidata.org/wiki/Q30642","display_name":"Natural language processing","level":1,"score":0.4081000089645386},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3792000114917755},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.3287000060081482},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.3151000142097473},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.3073999881744385},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.30320000648498535},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.3009999990463257},{"id":"https://openalex.org/C42023084","wikidata":"https://www.wikidata.org/wiki/Q5249231","display_name":"Decision boundary","level":3,"score":0.29159998893737793},{"id":"https://openalex.org/C51632099","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Training set","level":2,"score":0.28780001401901245},{"id":"https://openalex.org/C116409475","wikidata":"https://www.wikidata.org/wiki/Q1385056","display_name":"External Data Representation","level":2,"score":0.2849000096321106},{"id":"https://openalex.org/C137293760","wikidata":"https://www.wikidata.org/wiki/Q3621696","display_name":"Language model","level":2,"score":0.27459999918937683},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.2651999890804291},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.26080000400543213}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2604.18162","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.18162","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2604.18162","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.18162","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Large":[0],"Language":[1],"Models":[2],"(LLMs)":[3],"have":[4],"recently":[5],"achieved":[6],"strong":[7],"performance":[8],"in":[9,57,134,190],"software":[10],"code":[11,73],"generation.":[12,168],"However,":[13],"applying":[14],"them":[15],"to":[16,110,114,128,163],"hardware":[17,58],"description":[18],"languages":[19],"(HDLs),":[20],"such":[21],"as":[22],"Verilog,":[23],"remains":[24],"challenging":[25],"because":[26],"high-quality":[27],"training":[28,100],"data":[29,96],"are":[30],"relatively":[31],"scarce.":[32],"In":[33,61,147],"practice,":[34],"LLM-generated":[35],"Verilog":[36,72],"often":[37],"contains":[38],"syntactic":[39],"or":[40,48],"structural":[41],"errors":[42],"that":[43,70,155,178],"either":[44],"cause":[45],"compilation":[46,192],"failures":[47],"produce":[49],"functionally":[50],"incorrect":[51],"designs,":[52],"which":[53],"limit":[54],"its":[55],"reliability":[56],"design":[59],"workflows.":[60],"this":[62],"work,":[63],"we":[64,149],"propose":[65],"VerilogCL,":[66],"an":[67],"integrated":[68],"framework":[69],"enhances":[71],"generation":[74],"by":[75],"explicitly":[76],"learning":[77,87,127],"the":[78,112,135,139,183],"boundary":[79,133],"between":[80,118,141],"correct":[81,103,119,142],"and":[82,88,105,120,143,175,187,195],"erroneous":[83,108,121,144],"RTL":[84,104,109,145],"through":[85],"contrastive":[86,126],"proactive":[89,152],"error":[90],"screening.":[91],"Our":[92],"approach":[93],"introduces":[94],"minimal-error":[95],"augmentation,":[97],"generating":[98],"paired":[99],"samples":[101],"of":[102],"minimally":[106],"perturbed":[107],"teach":[111],"model":[113,181],"recognize":[115],"fine-grained":[116],"distinctions":[117],"code.":[122,146],"We":[123],"then":[124],"apply":[125],"learn":[129],"a":[130,151],"clearer":[131],"validity":[132],"representation":[136],"space,":[137],"improving":[138],"separation":[140],"addition,":[148],"introduce":[150],"screening":[153],"module":[154],"combines":[156],"semantic":[157],"embeddings":[158],"with":[159],"token-level":[160],"uncertainty":[161],"features":[162],"filter":[164],"low-confidence":[165],"candidates":[166],"during":[167],"Experiments":[169],"on":[170],"public":[171],"benchmarks,":[172],"including":[173],"VerilogEval":[174],"RTLLM,":[176],"show":[177],"our":[179],"7B-parameter":[180],"outperforms":[182],"evaluated":[184],"open-source,":[185],"Verilog-specialized,":[186],"commercial":[188],"baselines":[189],"both":[191],"success":[193],"rate":[194],"functional":[196],"correctness.":[197]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-04-22T00:00:00"}
