{"id":"https://openalex.org/W7154133935","doi":"https://doi.org/10.48550/arxiv.2604.08705","title":"qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking","display_name":"qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking","publication_year":2026,"publication_date":"2026-04-09","ids":{"openalex":"https://openalex.org/W7154133935","doi":"https://doi.org/10.48550/arxiv.2604.08705"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2604.08705","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.08705","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2604.08705","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027304745","display_name":"Robert S. Aviles","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Aviles, Robert S.","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075813371","display_name":"Ziyu Liu","orcid":"https://orcid.org/0000-0003-1166-3742"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liu, Ziyu","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030070995","display_name":"Jingkai Hong","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hong, Jingkai","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5133481106","display_name":"Sasan Razmkhah","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Razmkhah, Sasan","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5133518490","display_name":"Massoud Pedram","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pedram, Massoud","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5084205024","display_name":"Peter A. Beerel","orcid":"https://orcid.org/0000-0002-8283-0168"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Beerel, Peter A.","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5027304745"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.32280001044273376,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.32280001044273376,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.15809999406337738,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.1542000025510788,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5539000034332275},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4909000098705292},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.49070000648498535},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.47929999232292175},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.47540000081062317},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4431999921798706},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4108999967575073},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.39640000462532043},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.3944999873638153},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.361299991607666}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6121000051498413},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5539000034332275},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4909000098705292},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.49070000648498535},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4851999878883362},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.47929999232292175},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.47540000081062317},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4431999921798706},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4108999967575073},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.39640000462532043},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.3944999873638153},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.361299991607666},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.35690000653266907},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3546000123023987},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3474999964237213},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34139999747276306},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.33730000257492065},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.33469998836517334},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.29440000653266907},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.29350000619888306},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29179999232292175},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.2858999967575073},{"id":"https://openalex.org/C58053490","wikidata":"https://www.wikidata.org/wiki/Q176555","display_name":"Quantum computer","level":3,"score":0.2849999964237213},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2809999883174896},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.2754000127315521},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.27250000834465027},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.27000001072883606},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.26570001244544983},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26460000872612},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25699999928474426},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.2524000108242035},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.2515000104904175}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2604.08705","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.08705","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2604.08705","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2604.08705","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9043725728988647,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Adiabatic":[0],"Quantum-Flux-Parametron":[1],"(AQFP)":[2],"logic":[3,8],"is":[4],"an":[5],"ultra-low-power":[6],"superconducting":[7],"family":[9],"with":[10],"energy":[11],"consumption":[12],"approaching":[13],"the":[14,97],"Shannon":[15],"limit,":[16],"making":[17],"it":[18],"attractive":[19],"for":[20],"quantum":[21],"computing":[22,26],"control":[23],"and":[24,42,51,67,84,103,123],"cryogenic":[25],"systems.":[27],"Traditional":[28],"AQFP":[29,59,101],"designs":[30],"face":[31],"significant":[32],"physical":[33],"design":[34],"challenges":[35],"due":[36],"to":[37,47,63],"strict":[38],"gate-level":[39],"clocking":[40,57],"requirements":[41],"limited":[43],"interconnect":[44],"lengths,":[45],"leading":[46],"substantial":[48],"buffer":[49,152],"overhead":[50],"difficult":[52],"timing":[53,65,91,124,137],"closure.":[54],"Recently,":[55],"delay-line":[56],"of":[58,100,142],"has":[60,79],"been":[61],"proposed":[62],"improve":[64],"margins":[66],"reduce":[68],"latency":[69,85],"by":[70,154,163],"enabling":[71],"more":[72],"flexible":[73],"clock":[74,120],"scheduling.":[75],"However,":[76],"prior":[77],"work":[78],"primarily":[80],"focused":[81],"on":[82,89,156],"placement":[83],"minimization,":[86],"while":[87,158],"relying":[88],"fixed":[90],"parameters":[92],"that":[93,117],"do":[94],"not":[95],"capture":[96],"frequency":[98,162],"dependence":[99],"setup":[102],"hold":[104],"constraints.":[105],"To":[106],"address":[107],"this":[108],"limitation,":[109],"we":[110],"propose":[111],"a":[112,140],"frequency-aware":[113],"post-routing":[114,136],"optimization":[115],"framework":[116],"jointly":[118],"optimizes":[119],"period,":[121],"latency,":[122],"slack":[125],"under":[126],"user-specified":[127],"weighting.":[128],"Experimental":[129],"results":[130],"across":[131,139],"common":[132],"benchmarks":[133],"achieve":[134],"100%":[135],"closure":[138],"range":[141],"performance--latency--slack":[143],"trade-offs.":[144],"Our":[145],"approach":[146],"also":[147],"automates":[148],"phase-skipping,":[149],"reducing":[150,160],"path-balancing":[151],"insertion":[153],"34%":[155],"average":[157],"only":[159],"operating":[161],"4%.":[164]},"counts_by_year":[],"updated_date":"2026-04-14T06:08:25.285971","created_date":"2026-04-14T00:00:00"}