{"id":"https://openalex.org/W7138925530","doi":"https://doi.org/10.48550/arxiv.2603.16490","title":"ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM","display_name":"ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM","publication_year":2026,"publication_date":"2026-03-17","ids":{"openalex":"https://openalex.org/W7138925530","doi":"https://doi.org/10.48550/arxiv.2603.16490"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2603.16490","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.16490","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2603.16490","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022610117","display_name":"Alexander Zuepke","orcid":"https://orcid.org/0000-0003-0134-318X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zuepke, Alexander","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5129987127","display_name":"Ashutosh Pradhan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pradhan, Ashutosh","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130062438","display_name":"Daniele Ottaviano","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ottaviano, Daniele","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046241188","display_name":"Andrea Bastoni","orcid":"https://orcid.org/0000-0001-8256-6160"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bastoni, Andrea","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5129777394","display_name":"Marco Caccamo","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Caccamo, Marco","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.38339999318122864,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.38339999318122864,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.2046000063419342,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1573999971151352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.7455999851226807},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6913999915122986},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.590399980545044},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5828999876976013},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5784000158309937},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5239999890327454},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.476500004529953},{"id":"https://openalex.org/keywords/tracing","display_name":"Tracing","score":0.4611000120639801}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7793999910354614},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.7455999851226807},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6913999915122986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5990999937057495},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.590399980545044},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5828999876976013},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5784000158309937},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5239999890327454},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.476500004529953},{"id":"https://openalex.org/C138673069","wikidata":"https://www.wikidata.org/wiki/Q322229","display_name":"Tracing","level":2,"score":0.4611000120639801},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.4440999925136566},{"id":"https://openalex.org/C2777655017","wikidata":"https://www.wikidata.org/wiki/Q1501161","display_name":"Toolbox","level":2,"score":0.39419999718666077},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3653999865055084},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.3434000015258789},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.33820000290870667},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3368000090122223},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33500000834465027},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.31869998574256897},{"id":"https://openalex.org/C2778291847","wikidata":"https://www.wikidata.org/wiki/Q1163937","display_name":"Macrocell","level":3,"score":0.30649998784065247},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2872999906539917},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.28380000591278076},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.2809999883174896},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.2750000059604645},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.26030001044273376}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2603.16490","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.16490","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2603.16490","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.16490","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0],"Embedded":[1],"Trace":[2],"Macrocell":[3],"(ETM)":[4],"is":[5,146],"a":[6,15,39,46,100,115],"standard":[7],"component":[8],"of":[9,18,73,81,93,103,135],"Arm's":[10],"CoreSight":[11],"architecture,":[12],"present":[13],"in":[14,55,148],"wide":[16],"range":[17],"platforms":[19],"and":[20,25,48,64,75,78,91,107,138,154,164],"primarily":[21],"designed":[22],"for":[23],"tracing":[24],"debugging.":[26],"In":[27],"this":[28],"work,":[29],"we":[30,108],"demonstrate":[31],"that":[32,159],"it":[33,143],"can":[34],"be":[35],"repurposed":[36],"to":[37,51],"implement":[38],"novel":[40],"hardware-assisted":[41],"memory":[42,53,151],"bandwidth":[43,152],"regulator,":[44],"providing":[45],"portable":[47],"effective":[49,147],"solution":[50],"mitigate":[52],"interference":[54],"real-time":[56],"multicore":[57],"systems.":[58],"ETM2":[59,110,145],"requires":[60],"minimal":[61],"software":[62],"intervention":[63],"bridges":[65],"the":[66,69,76,89,119,126,133,136,140],"gap":[67],"between":[68],"fine-grained":[70],"microsecond":[71],"resolution":[72],"MemPol":[74],"portability":[77,92],"reaction":[79],"time":[80],"interrupt-based":[82],"solutions,":[83],"such":[84],"as":[85],"MemGuard.":[86],"We":[87],"assess":[88],"effectiveness":[90],"our":[94],"design":[95,141],"with":[96,111],"an":[97],"evaluation":[98],"on":[99,118,125],"large":[101],"number":[102],"64-bit":[104],"Arm":[105],"boards,":[106],"compare":[109],"previous":[112],"works":[113],"using":[114],"setup":[116],"based":[117],"San":[120],"Diego":[121],"Vision":[122],"Benchmark":[123],"Suite":[124],"AMD":[127],"Zynq":[128],"UltraScale+.":[129],"Our":[130],"results":[131],"show":[132],"scalability":[134],"approach":[137],"highlight":[139],"trade-offs":[142],"enables.":[144],"enforcing":[149],"per-core":[150],"regulation":[153,157],"unlocks":[155],"new":[156],"options":[158],"were":[160],"infeasible":[161],"under":[162],"MemGuard":[163],"MemPol.":[165]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-03-20T00:00:00"}
