{"id":"https://openalex.org/W7138203651","doi":"https://doi.org/10.48550/arxiv.2603.13665","title":"An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration","display_name":"An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration","publication_year":2026,"publication_date":"2026-03-14","ids":{"openalex":"https://openalex.org/W7138203651","doi":"https://doi.org/10.48550/arxiv.2603.13665"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2603.13665","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.13665","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2603.13665","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5129662051","display_name":"Chung-Kuan Cheng","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Cheng, Chung-Kuan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5129642930","display_name":"Andrew B. Kahng","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kahng, Andrew B.","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5129716743","display_name":"Bill Yuchen Lin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lin, Bill","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025893392","display_name":"Yucheng Wang","orcid":"https://orcid.org/0000-0002-8219-8908"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wang, Yucheng","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5129681245","display_name":"Dooseok Yoon","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yoon, Dooseok","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8586000204086304,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8586000204086304,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.047200001776218414,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.04659999907016754,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.7745000123977661},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.516700029373169},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.4722999930381775},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.45910000801086426},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4578000009059906},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.45750001072883606},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4235999882221222},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.3716999888420105}],"concepts":[{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.7745000123977661},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.516700029373169},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5088000297546387},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.4722999930381775},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.45910000801086426},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4578000009059906},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.45750001072883606},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4235999882221222},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37549999356269836},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.3716999888420105},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35499998927116394},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3529999852180481},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.3353999853134155},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.32519999146461487},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.31349998712539673},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3070000112056732},{"id":"https://openalex.org/C2983254600","wikidata":"https://www.wikidata.org/wiki/Q1096907","display_name":"Power grid","level":3,"score":0.3070000112056732},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2842999994754791},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.2833999991416931},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.26919999718666077},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.25949999690055847},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2590999901294708},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25220000743865967},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2515000104904175}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2603.13665","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.13665","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2603.13665","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.13665","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Advanced":[0],"nodes":[1],"decouple":[2],"contacted":[3],"poly":[4],"pitch":[5,9],"(CPP)":[6],"and":[7,28,37,54,87,93,101,111,119],"lower-metal":[8],"to":[10,22,66,70,98],"improve":[11],"routability.":[12],"We":[13],"present":[14],"CPCell,":[15],"an":[16],"efficient":[17],"standard-cell":[18],"layout":[19],"generation":[20],"framework,":[21],"support":[23],"arbitrary":[24],"gear":[25],"ratio":[26],"(GR)":[27],"offset":[29,102],"parameters":[30],"through":[31],"a":[32,55],"fine-grained":[33],"layered":[34],"grid":[35],"graph":[36],"constraint-programming-based":[38],"placement-routing":[39],"co-optimization.":[40],"Layout":[41],"quality":[42],"is":[43],"improved":[44],"via":[45],"Middle-of-Line":[46],"routing,":[47],"M0":[48],"pin":[49,51],"enablement,":[50],"accessibility":[52],"constraints":[53],"weighted":[56],"multi-objective":[57],"formulation":[58],"that":[59],"jointly":[60],"optimizes":[61],"cell":[62],"layouts.":[63],"To":[64],"scale":[65],"netlists":[67],"with":[68],"up":[69],"48":[71],"transistors,":[72],"we":[73],"incorporate":[74],"acceleration":[75],"techniques":[76],"including":[77],"transistor":[78,81],"clustering,":[79],"identical":[80],"partitioning,":[82],"routing":[83],"lower":[84],"bound":[85],"tightening":[86],"early":[88],"termination":[89],"strategies.":[90],"Comprehensive":[91],"cell-level":[92],"block-level":[94],"studies":[95],"are":[96],"conducted":[97],"evaluate":[99],"GR":[100],"choices,":[103],"quantify":[104],"the":[105,108],"benefits":[106],"of":[107],"proposed":[109],"objectives":[110],"assess":[112],"their":[113],"impact":[114],"on":[115],"power,":[116],"performance,":[117],"area":[118],"IR-drop":[120],"outcomes.":[121]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-03-18T00:00:00"}
