{"id":"https://openalex.org/W7136570606","doi":"https://doi.org/10.48550/arxiv.2603.12308","title":"HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators","display_name":"HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators","publication_year":2026,"publication_date":"2026-03-12","ids":{"openalex":"https://openalex.org/W7136570606","doi":"https://doi.org/10.48550/arxiv.2603.12308"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2603.12308","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.12308","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2603.12308","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5093285962","display_name":"Philippe Sauter","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sauter, Philippe","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5129436227","display_name":"Thomas Benz","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Benz, Thomas","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052998498","display_name":"Paul Scheffler","orcid":"https://orcid.org/0000-0003-4230-1381"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Scheffler, Paul","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5129480780","display_name":"Luca Benini","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Benini, Luca","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7178999781608582,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7178999781608582,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09489999711513519,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.025800000876188278,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.7351999878883362},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6212999820709229},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6079999804496765},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5533999800682068},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47429999709129333},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4652999937534332},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.41029998660087585},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.36399999260902405}],"concepts":[{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.7351999878883362},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6624000072479248},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6212999820709229},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6079999804496765},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5914999842643738},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5533999800682068},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5252000093460083},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47429999709129333},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4652999937534332},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.41029998660087585},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.36399999260902405},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.3400999903678894},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.3310999870300293},{"id":"https://openalex.org/C155386361","wikidata":"https://www.wikidata.org/wiki/Q1649571","display_name":"Process control","level":3,"score":0.3043999969959259},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30169999599456787},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.30149999260902405},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29980000853538513},{"id":"https://openalex.org/C96535780","wikidata":"https://www.wikidata.org/wiki/Q5457561","display_name":"Flash memory emulator","level":5,"score":0.28690001368522644},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2800999879837036},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.26669999957084656},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.2635999917984009},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.2590000033378601},{"id":"https://openalex.org/C17500928","wikidata":"https://www.wikidata.org/wiki/Q959968","display_name":"Control system","level":2,"score":0.2556000053882599},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.2513999938964844}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2603.12308","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.12308","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2603.12308","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.12308","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Domain-Specific":[0],"architectures":[1],"with":[2,65],"accelerators":[3],"for":[4,49,69],"machine":[5],"learning":[6],"and":[7,15,52,56,103,155],"signal":[8],"processing":[9],"require":[10],"efficient":[11],"bulk":[12],"data":[13],"movement":[14],"high-bandwidth":[16],"access":[17,55],"to":[18,36,80],"large":[19],"datasets.":[20],"Such":[21],"capabilities":[22],"are":[23],"often":[24],"absent":[25],"from":[26,136],"minimal":[27],"open-source":[28,39,101],"microcontrollers":[29],"(MCUs).":[30],"We":[31,130],"present":[32],"HyperCroc,":[33],"an":[34],"extension":[35],"the":[37,88,116,138,144,157],"end-to-end":[38,158],"RISC-V":[40],"Croc":[41,140],"system-on-chip":[42],"(SoC)":[43],"integrating":[44],"a":[45,57,61,74,127],"silicon-proven":[46],"HyperBus":[47,72],"controller":[48],"off-chip":[50],"DRAM":[51],"Flash":[53],"memory":[54],"DMA":[58,89],"engine,":[59],"providing":[60],"practical":[62],"MCU-class":[63],"platform":[64],"streamlined":[66],"plug-in":[67],"support":[68],"domain-specific":[70],"acceleration.":[71],"offers":[73],"low-pin-count":[75],"PSDRAM":[76],"interface":[77],"at":[78,149],"up":[79],"400":[81],"MB/s,":[82],"enabling":[83],"bandwidth-scaled":[84],"dataset":[85],"access,":[86],"while":[87],"engine":[90],"enables":[91],"autonomous,":[92],"high-throughput":[93],"transfers":[94],"without":[95],"CPU":[96],"intervention.":[97],"HyperCroc":[98],"preserves":[99],"Croc's":[100],"synthesis":[102],"physical":[104],"implementation":[105],"flow":[106],"targeting":[107],"IHP's":[108],"open":[109],"130":[110],"nm":[111],"process":[112],"design":[113],"kit":[114],"(PDK);":[115],"full":[117],"chip":[118],"can":[119],"be":[120],"implemented":[121],"in":[122],"under":[123],"one":[124],"hour":[125],"on":[126],"consumer-grade":[128],"workstation.":[129],"further":[131],"report":[132],"first":[133,139],"silicon":[134,145],"measurements":[135],"MLEM,":[137],"tapeout,":[141],"confirming":[142],"that":[143],"is":[146],"fully":[147],"functional":[148],"72":[150],"MHz":[151],"@":[152],"1.2":[153],"V":[154],"validating":[156],"flow.":[159]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-03-17T00:00:00"}