{"id":"https://openalex.org/W7135237199","doi":"https://doi.org/10.48550/arxiv.2603.11849","title":"Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs","display_name":"Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs","publication_year":2026,"publication_date":"2026-03-12","ids":{"openalex":"https://openalex.org/W7135237199","doi":"https://doi.org/10.48550/arxiv.2603.11849"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2603.11849","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.11849","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2603.11849","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5128934056","display_name":"Axel Vanoni","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vanoni, Axel","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093285962","display_name":"Philippe Sauter","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sauter, Philippe","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052998498","display_name":"Paul Scheffler","orcid":"https://orcid.org/0000-0003-4230-1381"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Scheffler, Paul","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128962115","display_name":"Anton Buchner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Buchner, Anton","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093751908","display_name":"Micha Wehrli","orcid":"https://orcid.org/0009-0004-0581-6487"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wehrli, Micha","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085591358","display_name":"Thomas Benz","orcid":"https://orcid.org/0000-0002-0326-9676"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Benz, Thomas","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5128984813","display_name":"Luca Benini","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Benini, Luca","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.4440000057220459,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.4440000057220459,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.37929999828338623,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.060600001364946365,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5776000022888184},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.5307999849319458},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5045999884605408},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5034000277519226},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.503000020980835},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.47859999537467957},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4625000059604645},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4580000042915344}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7296000123023987},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7077000141143799},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.6269000172615051},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5776000022888184},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.5307999849319458},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5045999884605408},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5034000277519226},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.503000020980835},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.47859999537467957},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4625000059604645},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4580000042915344},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38839998841285706},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.38260000944137573},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.3447999954223633},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3305000066757202},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.32589998841285706},{"id":"https://openalex.org/C50954386","wikidata":"https://www.wikidata.org/wiki/Q656083","display_name":"Paging","level":2,"score":0.3188999891281128},{"id":"https://openalex.org/C527821871","wikidata":"https://www.wikidata.org/wiki/Q228502","display_name":"Access control","level":2,"score":0.28369998931884766},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.28040000796318054},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2793000042438507},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.27129998803138733},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.25940001010894775},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.25220000743865967},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.2513999938964844}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2603.11849","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.11849","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2603.11849","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.11849","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Recent":[0],"announcements":[1],"have":[2],"shown":[3],"the":[4,46,81,117,125,130,148,173,178,187],"viability":[5],"of":[6,99,124,177,189],"end-to-end":[7,82],"open-source":[8,66],"(OS)":[9],"Linux-capable":[10],"RISC-V":[11,67,85,118],"systems":[12],"on":[13,135],"chip":[14],"(SoCs).":[15],"However,":[16],"practical":[17],"application":[18],"and":[19,90,103,121,132,153,181],"software":[20,92],"development":[21],"platforms":[22],"require":[23],"efficient":[24,56],"non-volatile":[25],"storage,":[26],"which":[27,128],"is":[28,62],"not":[29],"adequately":[30],"served":[31],"by":[32,116],"common":[33],"SPI-based":[34,190],"interfaces":[35],"due":[36],"to":[37,168,184],"their":[38],"limited":[39],"throughput.":[40],"Secure":[41],"Digital":[42],"(SD)":[43],"cards":[44],"are":[45,94,144],"de":[47],"facto":[48],"standard":[49],"storage":[50],"medium":[51],"for":[52,65],"embedded":[53],"Linux":[54,104],"systems;":[55],"SD":[57,73,179],"host":[58,74],"controller":[59,75,89,165],"(SDHC)":[60],"integration":[61],"thus":[63],"essential":[64],"platforms.":[68],"We":[69],"present":[70],"an":[71],"OS":[72,83,164],"interface":[76,180],"(SDHCI)":[77],"peripheral":[78],"integrated":[79],"into":[80],"Cheshire":[84],"SoC":[86],"platform.":[87],"The":[88],"its":[91],"stack":[93],"designed":[95],"with":[96],"full":[97],"awareness":[98],"CVA6's":[100,122],"memory":[101,119],"system":[102],"driver":[105],"behavior;":[106],"during":[107],"evaluation,":[108],"we":[109,157],"identify":[110],"a":[111],"significant":[112],"performance":[113],"bottleneck":[114],"caused":[115],"model":[120],"implementation":[123],"fence":[126],"instruction,":[127],"flushes":[129],"pipeline":[131],"data":[133],"cache":[134,140],"memory-mapped":[136],"register":[137,150],"accesses":[138],"when":[139],"management":[141],"operations":[142],"(CMOs)":[143],"unavailable.":[145],"By":[146],"customizing":[147],"driver's":[149],"access":[151],"paths":[152],"avoiding":[154],"unnecessary":[155],"fences,":[156],"substantially":[158],"reduced":[159],"this":[160],"overhead.":[161],"Our":[162],"fully":[163],"achieves":[166],"up":[167,183],"11.1":[169],"MB/s":[170,175],"throughput,":[171],"approaching":[172],"12.5":[174],"limit":[176],"providing":[182],"6.5":[185],"times":[186],"throughput":[188],"storage.":[191]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-03-14T00:00:00"}