{"id":"https://openalex.org/W7134055802","doi":"https://doi.org/10.48550/arxiv.2603.04646","title":"HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation","display_name":"HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation","publication_year":2026,"publication_date":"2026-03-04","ids":{"openalex":"https://openalex.org/W7134055802","doi":"https://doi.org/10.48550/arxiv.2603.04646"},"language":null,"primary_location":{"id":"pmh:doi:10.48550/arxiv.2603.04646","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":null,"any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5128250100","display_name":"Armin Abdollahi","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Abdollahi, Armin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128261342","display_name":"Saeid Shokoufa","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shokoufa, Saeid","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128230730","display_name":"Negin Ashrafi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ashrafi, Negin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042809860","display_name":"Mehdi Kamal","orcid":"https://orcid.org/0000-0001-7098-6440"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kamal, Mehdi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5128254240","display_name":"Massoud Pedram","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pedram, Massoud","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5128250100"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.07500000298023224,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.07500000298023224,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.048500001430511475,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.04179999977350235,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.640999972820282},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5680999755859375},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.47450000047683716},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.46880000829696655},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.39010000228881836},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.3075000047683716},{"id":"https://openalex.org/keywords/universal-asynchronous-receiver/transmitter","display_name":"Universal asynchronous receiver/transmitter","score":0.2858000099658966}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7706000208854675},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.640999972820282},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5680999755859375},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5300999879837036},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.48899999260902405},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.47450000047683716},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.46880000829696655},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.39010000228881836},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.3075000047683716},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29499998688697815},{"id":"https://openalex.org/C161911788","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Universal asynchronous receiver/transmitter","level":3,"score":0.2858000099658966},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.28380000591278076},{"id":"https://openalex.org/C61797465","wikidata":"https://www.wikidata.org/wiki/Q1188986","display_name":"Term (time)","level":2,"score":0.2720000147819519},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.2711000144481659},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.2619999945163727},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.25589999556541443},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.2556000053882599},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.25360000133514404}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:doi:10.48550/arxiv.2603.04646","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"doi:10.48550/arxiv.2603.04646","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2603.04646","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"pmh:doi:10.48550/arxiv.2603.04646","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6105215549468994}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"We":[0],"present":[1],"HDLFORGE,":[2],"a":[3,23,27,37,51,67],"two-stage":[4],"multi-agent":[5],"framework":[6],"for":[7],"automated":[8],"Verilog":[9,93],"generation":[10,16],"that":[11,71],"optimizes":[12],"the":[13],"trade-off":[14],"between":[15],"speed":[17],"and":[18,34,60,83,106,127,133,139,155],"accuracy.":[19],"The":[20,86],"system":[21],"uses":[22],"compact":[24],"coder":[25,39],"with":[26,40,142],"medium-sized":[28,153],"LLM":[29,43,94],"by":[30,50],"default":[31],"(Stage":[32,44],"A)":[33],"escalates":[35],"to":[36,115],"stronger":[38],"an":[41],"ultra-large":[42],"B)":[45],"only":[46],"when":[47],"needed,":[48],"guided":[49],"calibrated":[52],"score":[53],"from":[54],"inexpensive":[55],"diagnostics":[56],"including":[57],"compilation,":[58],"lint,":[59],"smoke":[61],"tests.":[62],"A":[63],"key":[64],"innovation":[65],"is":[66],"counterexample-guided":[68],"formal":[69],"agent":[70,128],"converts":[72],"bounded-model-checking":[73],"traces":[74],"into":[75],"reusable":[76],"micro-tests,":[77],"significantly":[78],"reducing":[79],"bug":[80],"detection":[81],"time":[82,123],"repair":[84],"iterations.":[85],"portable":[87],"escalation":[88,125],"controller":[89],"can":[90],"wrap":[91],"existing":[92],"pipelines":[95],"without":[96],"modifying":[97],"their":[98],"internals.":[99],"Evaluated":[100],"on":[101,158],"VerilogEval":[102,104,131,134],"Human,":[103],"V2,":[105,135],"RTLLM":[107],"benchmarks,":[108],"HDLFORGE":[109],"demonstrates":[110],"improved":[111],"accuracy-latency":[112],"trade-offs":[113],"compared":[114],"single-stage":[116],"systems":[117],"through":[118],"comprehensive":[119],"analysis":[120],"of":[121],"wall-clock":[122],"distributions,":[124],"thresholds,":[126],"ablations.":[129],"On":[130],"Human":[132],"HDLFORGE-Qwen":[136],"achieves":[137],"91.2%":[138],"91.8%":[140],"Pass@1":[141],"roughly":[143],"50%":[144],"lower":[145],"median":[146],"latency,":[147],"dramatically":[148],"improving":[149],"accuracy":[150],"over":[151],"other":[152],"models,":[154],"97.2%":[156],"Pass@5":[157],"RTLLM.":[159]},"counts_by_year":[],"updated_date":"2026-05-03T08:25:01.440150","created_date":"2026-03-07T00:00:00"}