{"id":"https://openalex.org/W7128375836","doi":"https://doi.org/10.48550/arxiv.2602.06085","title":"LAAFD: LLM-based Agents for Accelerated FPGA Design","display_name":"LAAFD: LLM-based Agents for Accelerated FPGA Design","publication_year":2026,"publication_date":"2026-02-04","ids":{"openalex":"https://openalex.org/W7128375836","doi":"https://doi.org/10.48550/arxiv.2602.06085"},"language":null,"primary_location":{"id":"pmh:doi:10.48550/arxiv.2602.06085","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"publisher-specific-oa","license_id":"https://openalex.org/licenses/publisher-specific-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":null,"any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5125397350","display_name":"Maxim Moraru","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Moraru, Maxim","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125385709","display_name":"Kamalavasan Kamalakkannan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kamalakkannan, Kamalavasan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"Dominguez-Trujillo, Jered","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dominguez-Trujillo, Jered","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121115142","display_name":"Patrick Diehl","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Diehl, Patrick","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"Barai, Atanu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Barai, Atanu","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125400002","display_name":"Julien Loiseau","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Loiseau, Julien","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125424898","display_name":"Zachary Kent Baker","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Baker, Zachary Kent","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044867580","display_name":"Howard Pritchard","orcid":"https://orcid.org/0000-0003-1969-0403"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pritchard, Howard","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":null,"display_name":"Shipman, Galen M","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shipman, Galen M","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5125397350"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9326000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9326000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.041099999099969864,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.004800000227987766,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8830999732017517},{"id":"https://openalex.org/keywords/stencil","display_name":"Stencil","score":0.6435999870300293},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.6416000127792358},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5990999937057495},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5781999826431274},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5587999820709229},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5558000206947327},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5266000032424927},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.4627000093460083},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.43059998750686646}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8830999732017517},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.794700026512146},{"id":"https://openalex.org/C76752949","wikidata":"https://www.wikidata.org/wiki/Q7607499","display_name":"Stencil","level":2,"score":0.6435999870300293},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.6416000127792358},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5990999937057495},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5781999826431274},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5587999820709229},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5558000206947327},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5266000032424927},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4961000084877014},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4627000093460083},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.43059998750686646},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.42980000376701355},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.39590001106262207},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3912999927997589},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3833000063896179},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.33889999985694885},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.32120001316070557},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.30970001220703125},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.30000001192092896},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2948000133037567},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29429998993873596},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.2928999960422516},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.2897999882698059},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.2775999903678894},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.2759999930858612},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.2734000086784363},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.26600000262260437},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.26030001044273376},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.25929999351501465},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.257099986076355},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.2565999925136566},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.25519999861717224},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.2533999979496002},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.2522999942302704}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:doi:10.48550/arxiv.2602.06085","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"publisher-specific-oa","license_id":"https://openalex.org/licenses/publisher-specific-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"doi:10.48550/arxiv.2602.06085","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2602.06085","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"pmh:doi:10.48550/arxiv.2602.06085","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"publisher-specific-oa","license_id":"https://openalex.org/licenses/publisher-specific-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.889528214931488}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"FPGAs":[0],"offer":[1],"high":[2],"performance,":[3],"low":[4],"latency,":[5],"and":[6,16,41,73,76,83],"energy":[7],"efficiency":[8],"for":[9,120,138],"accelerated":[10],"computing,":[11],"yet":[12],"adoption":[13],"in":[14,94,106],"scientific":[15],"edge":[17],"settings":[18],"is":[19],"limited":[20],"by":[21],"the":[22,78,116,128,152],"specialized":[23],"hardware":[24],"expertise":[25,153],"required.":[26],"High-level":[27],"synthesis":[28,84],"(HLS)":[29],"boosts":[30],"productivity":[31],"over":[32],"HDLs,":[33],"but":[34],"competitive":[35],"designs":[36],"still":[37],"demand":[38],"hardware-aware":[39],"optimizations":[40],"careful":[42],"dataflow":[43,74],"design.":[44],"We":[45],"introduce":[46],"LAAFD,":[47],"an":[48],"agentic":[49],"workflow":[50],"that":[51],"uses":[52],"large":[53],"language":[54],"models":[55],"to":[56,86,115,155],"translate":[57],"general-purpose":[58],"C++":[59],"into":[60],"optimized":[61],"Vitis":[62,121],"HLS":[63,81,135],"kernels.":[64,145],"LAAFD":[65,126,149],"automates":[66],"key":[67],"transfor":[68],"mations:":[69],"deep":[70],"pipelining,":[71],"vectorization,":[72],"partitioning":[75],"closes":[77],"loop":[79],"with":[80],"co-simulation":[82],"feedback":[85],"verify":[87],"correctness":[88],"while":[89,141],"iteratively":[90],"improving":[91],"execution":[92],"time":[93],"cycles.":[95],"Over":[96],"a":[97,132],"suite":[98],"of":[99,130],"15":[100],"kernels":[101],"representing":[102],"common":[103],"compute":[104],"patterns":[105],"HPC,":[107],"LAFFD":[108],"achieves":[109],"99.9%":[110],"geomean":[111],"performance":[112,129],"when":[113],"compared":[114],"hand":[117],"tuned":[118],"baseline":[119],"HLS.":[122],"For":[123],"stencil":[124,139],"workloads,":[125],"matches":[127],"SODA,":[131],"state-of-the-art":[133],"DSL-based":[134],"code":[136],"generator":[137],"solvers,":[140],"yielding":[142],"more":[143],"readable":[144],"These":[146],"results":[147],"suggest":[148],"substantially":[150],"lowers":[151],"barrier":[154],"FPGA":[156],"acceleration":[157],"without":[158],"sacrificing":[159],"efficiency.":[160]},"counts_by_year":[],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2026-02-10T00:00:00"}
