{"id":"https://openalex.org/W7126203225","doi":"https://doi.org/10.48550/arxiv.2601.22151","title":"Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing","display_name":"Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing","publication_year":2026,"publication_date":"2026-01-29","ids":{"openalex":"https://openalex.org/W7126203225","doi":"https://doi.org/10.48550/arxiv.2601.22151"},"language":null,"primary_location":{"id":"pmh:doi:10.48550/arxiv.2601.22151","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":null,"any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5124302643","display_name":"Daniel Stein","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Stein, Daniel","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124346403","display_name":"Shaoyi Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Huang, Shaoyi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124343795","display_name":"Rolf Drechsler","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Drechsler, Rolf","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124302414","display_name":"Bing Li","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Li, Bing","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5070194930","display_name":"Grace Li Zhang","orcid":"https://orcid.org/0000-0002-8289-9288"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhang, Grace Li","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08361814,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.2393999993801117,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.2393999993801117,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.14259999990463257,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.1266999989748001,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6312000155448914},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5648999810218811},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4417000114917755},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.39879998564720154},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3555999994277954},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.34700000286102295},{"id":"https://openalex.org/keywords/edge-device","display_name":"Edge device","score":0.33970001339912415},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.31839999556541443}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7638000249862671},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6312000155448914},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5648999810218811},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4417000114917755},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.39879998564720154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3560999929904938},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3555999994277954},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.34700000286102295},{"id":"https://openalex.org/C138236772","wikidata":"https://www.wikidata.org/wiki/Q25098575","display_name":"Edge device","level":3,"score":0.33970001339912415},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3337000012397766},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33149999380111694},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.31839999556541443},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.3100000023841858},{"id":"https://openalex.org/C150495011","wikidata":"https://www.wikidata.org/wiki/Q128392","display_name":"Concurrent computing","level":2,"score":0.30309998989105225},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2973000109195709},{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.290800005197525},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.27970001101493835},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.2775999903678894},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.27709999680519104},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.2653000056743622},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.258899986743927},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.2542000114917755}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:doi:10.48550/arxiv.2601.22151","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"doi:10.48550/arxiv.2601.22151","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2601.22151","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:doi:10.48550/arxiv.2601.22151","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Neural":[0],"networks":[1,76,94],"have":[2],"been":[3],"successfully":[4],"applied":[5],"in":[6,79],"various":[7],"resource-constrained":[8],"edge":[9],"devices,":[10],"where":[11],"usually":[12],"central":[13],"processing":[14,20],"units":[15,21],"(CPUs)":[16],"instead":[17],"of":[18,37,74,121,130],"graphics":[19],"exist":[22],"due":[23],"to":[24,61,84,144],"limited":[25],"power":[26],"availability.":[27],"State-of-the-art":[28],"research":[29],"still":[30],"focuses":[31],"on":[32,52,77,147],"efficiently":[33],"executing":[34,48],"enormous":[35],"numbers":[36],"multiply-accumulate":[38],"(MAC)":[39],"operations.":[40,132],"However,":[41],"CPUs":[42],"themselves":[43],"are":[44,58,95,109],"not":[45],"good":[46],"at":[47,161],"such":[49],"mathematical":[50],"operations":[51],"a":[53,127,148],"large":[54],"scale,":[55],"since":[56],"they":[57],"more":[59],"suited":[60],"execute":[62],"control":[63],"flow":[64],"logic,":[65],"i.e.,":[66],"computer":[67],"algorithms.":[68],"To":[69],"enhance":[70],"the":[71,137],"computation":[72],"efficiency":[73],"neural":[75,93],"CPUs,":[78],"this":[80],"paper,":[81],"we":[82],"propose":[83],"convert":[85],"them":[86],"into":[87,98,114],"logic":[88,115,118],"flows":[89,119],"for":[90],"execution.":[91],"Specifically,":[92],"first":[96],"converted":[97],"equivalent":[99],"decision":[100,104],"trees,":[101],"from":[102],"which":[103],"paths":[105],"with":[106],"constant":[107],"leaves":[108],"then":[110],"selected":[111],"and":[112,123,126],"compressed":[113],"flows.":[116],"Such":[117],"consist":[120],"if":[122],"else":[124],"structures":[125],"reduced":[128,141],"number":[129],"MAC":[131],"Experimental":[133],"results":[134],"demonstrate":[135],"that":[136],"latency":[138],"can":[139],"be":[140],"by":[142],"up":[143],"14.9":[145],"%":[146],"simulated":[149],"RISC-V":[150],"CPU":[151],"without":[152],"any":[153],"accuracy":[154],"degradation.":[155],"The":[156],"code":[157],"is":[158],"open":[159],"source":[160],"https://github.com/TUDa-HWAI/NN2Logic":[162]},"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2026-02-01T00:00:00"}