{"id":"https://openalex.org/W7123894406","doi":"https://doi.org/10.48550/arxiv.2601.07069","title":"Neuromorphic FPGA Design for Digital Signal Processing","display_name":"Neuromorphic FPGA Design for Digital Signal Processing","publication_year":2026,"publication_date":"2026-01-11","ids":{"openalex":"https://openalex.org/W7123894406","doi":"https://doi.org/10.48550/arxiv.2601.07069"},"language":null,"primary_location":{"id":"doi:10.48550/arxiv.2601.07069","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2601.07069","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"type":"preprint","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.48550/arxiv.2601.07069","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5122972324","display_name":"Justin London","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"London, Justin","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5122972324"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9564999938011169,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9564999938011169,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12611","display_name":"Neural Networks and Reservoir Computing","score":0.009200000204145908,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.008299999870359898,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.9887999892234802},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5109000205993652},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5078999996185303},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.49880000948905945},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4871000051498413},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.48010000586509705},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4634000062942505},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.42149999737739563}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.9887999892234802},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.732200026512146},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5365999937057495},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5109000205993652},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5078999996185303},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.49880000948905945},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4871000051498413},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.48010000586509705},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4634000062942505},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.42149999737739563},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.412200003862381},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.39980000257492065},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39649999141693115},{"id":"https://openalex.org/C23375383","wikidata":"https://www.wikidata.org/wiki/Q176499","display_name":"Unconventional computing","level":2,"score":0.3546999990940094},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.3495999872684479},{"id":"https://openalex.org/C72279823","wikidata":"https://www.wikidata.org/wiki/Q1139726","display_name":"Impulse response","level":2,"score":0.3450999855995178},{"id":"https://openalex.org/C183816354","wikidata":"https://www.wikidata.org/wiki/Q665617","display_name":"Infinite impulse response","level":4,"score":0.3427000045776367},{"id":"https://openalex.org/C70836080","wikidata":"https://www.wikidata.org/wiki/Q837940","display_name":"Impulse (physics)","level":2,"score":0.34049999713897705},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3402999937534332},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.321399986743927},{"id":"https://openalex.org/C11731999","wikidata":"https://www.wikidata.org/wiki/Q9067355","display_name":"Spiking neural network","level":3,"score":0.30230000615119934},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.27619999647140503},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.27320000529289246},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.27239999175071716},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.26429998874664307},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.26190000772476196}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.48550/arxiv.2601.07069","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2601.07069","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"doi:10.48550/arxiv.2601.07069","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2601.07069","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"},"sustainable_development_goals":[{"score":0.8963748812675476,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,93],"foundations":[4],"of":[5,95],"neuromorphic":[6,46,57,77],"computing,":[7],"spiking":[8],"neural":[9],"networks":[10],"(SNNs)":[11],"and":[12,16,35,44,62,74,88],"memristors,":[13],"are":[14,41],"analyzed":[15],"discussed.":[17],"Neuromorphic":[18],"computing":[19,47,58,78],"is":[20],"then":[21],"applied":[22],"to":[23,71],"FPGA":[24],"design":[25],"for":[26],"digital":[27],"signal":[28],"processing":[29],"(DSP).":[30],"Finite":[31],"impulse":[32,37],"response":[33,38],"(FIR)":[34],"infinite":[36],"(IIR)":[39],"filters":[40],"implemented":[42],"with":[43],"without":[45],"in":[48],"Vivado":[49],"using":[50],"Verilog":[51],"HDL.":[52],"The":[53],"results":[54],"suggest":[55],"that":[56],"can":[59,79],"provide":[60],"low-latency":[61],"synaptic":[63],"plasticity":[64],"thereby":[65],"enabling":[66],"continuous":[67],"on-chip":[68],"learning.":[69],"Due":[70],"their":[72],"parallel":[73],"event-driven":[75],"nature,":[76],"reduce":[80],"power":[81],"consumption":[82],"by":[83],"eliminating":[84],"von":[85],"Neumann":[86],"bottlenecks":[87],"improve":[89],"efficiency,":[90],"but":[91],"at":[92],"cost":[94],"reduced":[96],"numeric":[97],"precision.":[98]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2026-01-14T00:00:00"}