{"id":"https://openalex.org/W2080236872","doi":"https://doi.org/10.4304/jcp.5.9.1343-1347","title":"Functional Verification Methodology of Complex Electronics System Based Modeling and Simulation","display_name":"Functional Verification Methodology of Complex Electronics System Based Modeling and Simulation","publication_year":2010,"publication_date":"2010-09-02","ids":{"openalex":"https://openalex.org/W2080236872","doi":"https://doi.org/10.4304/jcp.5.9.1343-1347","mag":"2080236872"},"language":"en","primary_location":{"id":"doi:10.4304/jcp.5.9.1343-1347","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.5.9.1343-1347","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102856753","display_name":"Jianwu Wu","orcid":"https://orcid.org/0009-0004-8672-8381"},"institutions":[{"id":"https://openalex.org/I75900474","display_name":"Hubei University","ror":"https://ror.org/03a60m280","country_code":"CN","type":"education","lineage":["https://openalex.org/I75900474"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jianwu Wu","raw_affiliation_strings":["Hubei Univ"],"affiliations":[{"raw_affiliation_string":"Hubei Univ","institution_ids":["https://openalex.org/I75900474"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5102856753"],"corresponding_institution_ids":["https://openalex.org/I75900474"],"apc_list":null,"apc_paid":null,"fwci":0.7226,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.77766811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"5","issue":"9","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.9607552289962769},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8735212087631226},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7736745476722717},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7639850378036499},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.6401245594024658},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5519176125526428},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.5016894340515137},{"id":"https://openalex.org/keywords/modeling-and-simulation","display_name":"Modeling and simulation","score":0.4766412675380707},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3764001727104187},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.28002864122390747},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.25802081823349},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.256162166595459},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.18642431497573853},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08895888924598694},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08395460247993469}],"concepts":[{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.9607552289962769},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8735212087631226},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7736745476722717},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7639850378036499},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.6401245594024658},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5519176125526428},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.5016894340515137},{"id":"https://openalex.org/C167343916","wikidata":"https://www.wikidata.org/wiki/Q6888384","display_name":"Modeling and simulation","level":2,"score":0.4766412675380707},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3764001727104187},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.28002864122390747},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.25802081823349},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.256162166595459},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18642431497573853},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08895888924598694},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08395460247993469},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.4304/jcp.5.9.1343-1347","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.5.9.1343-1347","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1499857606","https://openalex.org/W2106090060","https://openalex.org/W2199041955","https://openalex.org/W2536181230"],"related_works":["https://openalex.org/W2599129971","https://openalex.org/W1544489228","https://openalex.org/W2167433763","https://openalex.org/W2018397012","https://openalex.org/W2401743419","https://openalex.org/W2363848262","https://openalex.org/W2666469582","https://openalex.org/W2041277225","https://openalex.org/W2083571437","https://openalex.org/W2240386274","https://openalex.org/W2553978230","https://openalex.org/W2074438289","https://openalex.org/W2399012645","https://openalex.org/W3123283247","https://openalex.org/W2399580665","https://openalex.org/W2386431351","https://openalex.org/W2384765745","https://openalex.org/W1505769163","https://openalex.org/W71406062","https://openalex.org/W2116517177"],"abstract_inverted_index":{"Nowadays":[0],"electronics":[1,27,91],"system":[2,28,36],"becomes":[3],"more":[4,6],"and":[5,22,54,63,68,86],"complex,":[7],"which":[8],"causes":[9],"difficulty":[10],"to":[11,25,42,84],"debug.":[12],"The":[13],"paper":[14],"presents":[15],"a":[16,81],"new":[17],"method":[18,48,79],"of":[19,46,89],"system-level":[20],"simulation":[21],"functional":[23,56,87],"verification":[24],"complex":[26,90],"by":[29,60,70],"modeling.":[30],"A":[31],"high-speed":[32],"image":[33],"real-time":[34],"storage":[35],"is":[37,58],"used":[38],"as":[39],"an":[40],"example":[41],"explain":[43],"the":[44,77],"application":[45],"modeling":[47],"in":[49,65],"actual":[50],"system,":[51],"each":[55],"module":[57],"modeled":[59],"Verilog":[61],"language":[62],"simulated":[64],"ModelSim":[66],"platform":[67],"verified":[69],"Matlab":[71],"platform.":[72],"Practice":[73],"has":[74,80],"proved":[75],"that":[76],"above-mentioned":[78],"good":[82],"benefit":[83],"debugging":[85],"verifying":[88],"system.":[92]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
