{"id":"https://openalex.org/W2148021111","doi":"https://doi.org/10.4304/jcp.9.5.1131-1137","title":"An Architecture Independent Packing Method for LUT-based Commercial FPGA","display_name":"An Architecture Independent Packing Method for LUT-based Commercial FPGA","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W2148021111","doi":"https://doi.org/10.4304/jcp.9.5.1131-1137","mag":"2148021111"},"language":"en","primary_location":{"id":"doi:10.4304/jcp.9.5.1131-1137","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.9.5.1131-1137","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005595160","display_name":"Meng Yang","orcid":"https://orcid.org/0000-0003-2862-2015"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Meng Yang","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5033888958","display_name":"A.E.A. Almaini","orcid":"https://orcid.org/0000-0002-7432-7730"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. E.A. Almaini","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005595160"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14103303,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":"5","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8173893690109253},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7330753803253174},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6541651487350464},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47003433108329773},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45755258202552795},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42334651947021484},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3866485357284546},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.372450590133667},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1622444987297058},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15817603468894958},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.0466667115688324}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8173893690109253},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7330753803253174},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6541651487350464},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47003433108329773},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45755258202552795},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42334651947021484},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3866485357284546},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.372450590133667},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1622444987297058},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15817603468894958},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0466667115688324},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.4304/jcp.9.5.1131-1137","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.9.5.1131-1137","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1963908543","https://openalex.org/W1967624322","https://openalex.org/W1977850862","https://openalex.org/W1981831650","https://openalex.org/W2004993081","https://openalex.org/W2021149030","https://openalex.org/W2055251702","https://openalex.org/W2095431940","https://openalex.org/W2111386963","https://openalex.org/W2111756578","https://openalex.org/W2137454730","https://openalex.org/W2138383740","https://openalex.org/W2139637699","https://openalex.org/W2147405597","https://openalex.org/W2155033206","https://openalex.org/W3141147179","https://openalex.org/W6651692632","https://openalex.org/W6676499570"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2990962948","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2155289750","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441"],"abstract_inverted_index":{"This":[0,125],"paper":[1],"proposes":[2],"an":[3],"efficient":[4],"architecture":[5,36,128],"independent":[6,129],"packing":[7],"method":[8,70,126],"for":[9,134],"commercial":[10,16,137,155],"FPGA.":[11],"All":[12],"specific":[13],"logics":[14],"of":[15,37,168],"FPGA":[17],"such":[18],"as":[19,139,141],"carry":[20],"chain":[21],"arithmetic,":[22],"x-LUT,":[23],"are":[24,106,146],"pre-designed":[25,72,143],"into":[26,108,119],"reference":[27,43,73,84,144],"circuits":[28,44,74,145],"according":[29],"to":[30,34,40,86],"its":[31],"architecture.":[32],"Due":[33],"complex":[35],"contemporary":[38],"FPGA,":[39],"enumerate":[41],"all":[42],"in":[45,59,121],"a":[46,122],"fine-grain":[47],"manner":[48,56],"is":[49,57,90,127],"impractical.":[50],"To":[51],"overcome":[52],"this":[53],"problem,":[54],"coarse-grain":[55],"adapted":[58],"the":[60,68,76,83,87,99,109,142,166,169],"approach.":[61],"By":[62],"using":[63,93],"constraint":[64],"satisfaction":[65],"problem":[66],"technique":[67],"proposed":[69,170],"matches":[71],"from":[75,82],"given":[77],"user":[78],"logic":[79],"circuit.":[80],"Transformation":[81],"circuit":[85],"pre-packed":[88,110],"cluster":[89],"simplified":[91],"by":[92],"several":[94],"specifically":[95],"designed":[96],"instructions.":[97],"In":[98],"next":[100],"stage,":[101],"those":[102],"directly":[103],"connected":[104],"FFs":[105,118],"absorbed":[107],"clusters.":[111],"The":[112,149],"Last":[113],"stage":[114],"packs":[115],"LUTs":[116],"and":[117,130,152,159],"clusters":[120],"delay-based":[123],"manner.":[124],"can":[131],"be":[132],"applied":[133],"any":[135],"other":[136],"FPGAs":[138],"long":[140],"modified":[147],"accordingly.":[148],"results":[150],"obtained":[151],"compared":[153],"with":[154],"tool,":[156,161],"ISE":[157],"MAP,":[158,163],"academic":[160],"PAM":[162],"have":[164],"shown":[165],"effectiveness":[167],"method.":[171]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}