{"id":"https://openalex.org/W2035337850","doi":"https://doi.org/10.4304/jcp.9.10.2359-2364","title":"A FPGA Stereo Matching Algorithm Modeled By DSP Builder","display_name":"A FPGA Stereo Matching Algorithm Modeled By DSP Builder","publication_year":2014,"publication_date":"2014-10-30","ids":{"openalex":"https://openalex.org/W2035337850","doi":"https://doi.org/10.4304/jcp.9.10.2359-2364","mag":"2035337850"},"language":"en","primary_location":{"id":"doi:10.4304/jcp.9.10.2359-2364","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.9.10.2359-2364","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100368885","display_name":"Xiang Zhang","orcid":"https://orcid.org/0000-0002-7543-8352"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiang Zhang","raw_affiliation_strings":["State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110076587","display_name":"Zhang Wei Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhang Wei Chen","raw_affiliation_strings":["State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100368885"],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.4943,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.69399029,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"9","issue":"10","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11105","display_name":"Advanced Image Processing Techniques","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7675862312316895},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6836602091789246},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6502696871757507},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.564192533493042},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45131799578666687},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3735611140727997},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30127549171447754},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11978477239608765}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7675862312316895},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6836602091789246},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6502696871757507},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.564192533493042},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45131799578666687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3735611140727997},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30127549171447754},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11978477239608765},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.4304/jcp.9.10.2359-2364","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.9.10.2359-2364","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.1004.6403","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1004.6403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.i-scholar.in/index.php/JOCACP/article/download/58022/49017/","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1863163046","https://openalex.org/W1964164722","https://openalex.org/W1976760299","https://openalex.org/W1979846720","https://openalex.org/W1989982732","https://openalex.org/W2063694420","https://openalex.org/W2093309804","https://openalex.org/W2104974755","https://openalex.org/W2117930911","https://openalex.org/W2125676951","https://openalex.org/W2136929315","https://openalex.org/W2159033218","https://openalex.org/W2163847543","https://openalex.org/W2170803817","https://openalex.org/W4231605664","https://openalex.org/W4233730708","https://openalex.org/W4236965008","https://openalex.org/W6673875518","https://openalex.org/W6678826710","https://openalex.org/W6684242597","https://openalex.org/W6685088491"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W3042736233","https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W2387078853","https://openalex.org/W2374455716","https://openalex.org/W2363990172"],"abstract_inverted_index":{"Abstract\u2014This":[0],"paper":[1],"proposes":[2],"a":[3,9,22,39,76],"System-on-Programmable-Chip":[4],"(SoPC)":[5],"architecture":[6],"to":[7],"implement":[8],"stereo":[10,47,53,72,84],"matching":[11,48,54],"algorithm":[12,49,55],"based":[13],"on":[14],"the":[15,60],"sum":[16],"of":[17,71,83],"absolute":[18],"differences":[19],"(SAD)":[20],"in":[21],"FPGA":[23],"chip":[24],"which":[25],"can":[26,66],"provide":[27],"1396\u00d71110":[28],"disparity":[29],"maps":[30],"at":[31],"30":[32],"fps":[33],"speed.":[34],"The":[35,52,64,79],"hardware":[36],"implementation":[37],"involves":[38],"32-bit":[40],"Nios":[41],"II":[42],"microprocessor,":[43],"memory":[44],"interfaces":[45],"and":[46],"circuit":[50],"module.":[51],"core":[56],"is":[57,86],"modeled":[58],"by":[59],"Matlab-based":[61],"DSP":[62],"Builder.":[63],"system":[65],"process":[67],"many":[68],"different":[69],"sizes":[70],"pair":[73],"images":[74,85],"through":[75],"configuration":[77],"interface.":[78],"maximum":[80],"horizon":[81],"resolution":[82],"2048.":[87],"Index":[88],"Terms\u2014Stereo":[89],"matching,":[90],"System-on-programmable-":[91]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}