{"id":"https://openalex.org/W2037556888","doi":"https://doi.org/10.4304/jcp.4.10.921-926","title":"DTMOS Based Low Power High Speed Interconnects for FPGA","display_name":"DTMOS Based Low Power High Speed Interconnects for FPGA","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2037556888","doi":"https://doi.org/10.4304/jcp.4.10.921-926","mag":"2037556888"},"language":"en","primary_location":{"id":"doi:10.4304/jcp.4.10.921-926","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.4.10.921-926","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087782629","display_name":"Kureshi Abdul Kadir","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kureshi Abdul Kadir","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":null,"display_name":"Mohd Hasan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mohd Hasan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6005,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.70717987,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"4","issue":"10","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6655097007751465},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6554732322692871},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.48080649971961975},{"id":"https://openalex.org/keywords/ultra-low-power","display_name":"Ultra low power","score":0.4219667315483093},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35588353872299194},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.16667723655700684},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08117499947547913}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6655097007751465},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6554732322692871},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.48080649971961975},{"id":"https://openalex.org/C3017773396","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Ultra low power","level":4,"score":0.4219667315483093},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35588353872299194},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.16667723655700684},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08117499947547913},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.4304/jcp.4.10.921-926","is_oa":false,"landing_page_url":"https://doi.org/10.4304/jcp.4.10.921-926","pdf_url":null,"source":{"id":"https://openalex.org/S77894049","display_name":"Journal of Computers","issn_l":"1796-203X","issn":["1796-203X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318660","host_organization_name":"Academy Publisher","host_organization_lineage":["https://openalex.org/P4310318660"],"host_organization_lineage_names":["Academy Publisher"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1480203124","https://openalex.org/W1523051745","https://openalex.org/W1604323946","https://openalex.org/W1719300925","https://openalex.org/W2018219387","https://openalex.org/W2108519747","https://openalex.org/W2138308719","https://openalex.org/W2155827627","https://openalex.org/W2159448561"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2111241003","https://openalex.org/W2390279801","https://openalex.org/W4200391368","https://openalex.org/W2358668433","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W2742986847"],"abstract_inverted_index":{"This":[0],"paper":[1],"present":[2],"new":[3],"energy":[4],"efficient":[5],"methods":[6],"of":[7,18,24,46,72,84,98,109,111],"designing":[8],"switches":[9,30],"and":[10,31,90],"routing":[11,44,101,114],"interconnects":[12,102],"inside":[13],"FPGA":[14,100,107],"using":[15],"novel":[16],"variants":[17],"Dynamic":[19],"Threshold":[20],"MOS":[21],"(DTMOS)":[22],"instead":[23],"traditional":[25],"NMOS":[26],"pass":[27,88],"transistor":[28,55],"based":[29,43,59,113],"interconnects.":[32],"The":[33],"extra":[34],"needed":[35],"transistors":[36],"can":[37],"be":[38,52],"easily":[39],"shared,":[40],"in":[41,79,95,120],"multiplexer":[42],"architecture":[45],"FPGA,":[47],"keeping":[48],"area":[49],"overhead":[50],"to":[51],"minimum.":[53],"Extensive":[54],"level":[56],"HSPICE":[57],"simulation":[58],"on":[60],"Berkeley":[61],"Predictive":[62],"Technology":[63],"Model":[64],"(BPTM)":[65],"for":[66],"65nm":[67],"device":[68],"at":[69],"operating":[70],"frequency":[71],"300MHz":[73],"shows":[74],"an":[75,91],"average":[76,92],"23.35%":[77],"improvement":[78,94,119],"power":[80],"delay":[81],"product":[82],"(PDP)":[83],"simple":[85],"switch":[86],"(NMOS":[87],"transistor)":[89],"32.83%":[93],"the":[96,117,121],"PDP":[97,122],"Virtex-II":[99],"over":[103],"conventional":[104],"approaches.":[105],"Since":[106],"consists":[108],"thousands":[110],"Multiplexer":[112],"interconnects,":[115],"hence":[116],"overall":[118],"is":[123],"significant.":[124]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
