{"id":"https://openalex.org/W2995619173","doi":"https://doi.org/10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","title":"Database Acceleration on FPGAs","display_name":"Database Acceleration on FPGAs","publication_year":2019,"publication_date":"2019-11-25","ids":{"openalex":"https://openalex.org/W2995619173","doi":"https://doi.org/10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","mag":"2995619173"},"language":"en","primary_location":{"id":"pmh:oai:tudelft.nl:uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","is_oa":false,"landing_page_url":"http://resolver.tudelft.nl/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","pdf_url":null,"source":{"id":"https://openalex.org/S4306400906","display_name":"Research Repository (Delft University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98358874","host_organization_name":"Delft University of Technology","host_organization_lineage":["https://openalex.org/I98358874"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"doctoral thesis"},"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038987393","display_name":"Jian Fang","orcid":"https://orcid.org/0000-0002-1077-1859"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Fang, J.","raw_affiliation_strings":["Computer Engineering"],"affiliations":[{"raw_affiliation_string":"Computer Engineering","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5038987393"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.28,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.6718715,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9740999937057495,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.963100016117096,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8076220750808716},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.773490309715271},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5154963135719299},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5091926455497742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48276248574256897},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.4726521074771881},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19726848602294922}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8076220750808716},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.773490309715271},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5154963135719299},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5091926455497742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48276248574256897},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.4726521074771881},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19726848602294922}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:tudelft.nl:uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","is_oa":false,"landing_page_url":"http://resolver.tudelft.nl/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","pdf_url":null,"source":{"id":"https://openalex.org/S4306400906","display_name":"Research Repository (Delft University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98358874","host_organization_name":"Delft University of Technology","host_organization_lineage":["https://openalex.org/I98358874"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"doctoral thesis"},{"id":"doi:10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","is_oa":true,"landing_page_url":"https://doi.org/10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","pdf_url":null,"source":{"id":"https://openalex.org/S4306400906","display_name":"Research Repository (Delft University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98358874","host_organization_name":"Delft University of Technology","host_organization_lineage":["https://openalex.org/I98358874"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"thesis"}],"best_oa_location":{"id":"doi:10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","is_oa":true,"landing_page_url":"https://doi.org/10.4233/uuid:84dfc577-ca6f-43ea-9b24-4dc160c103f5","pdf_url":null,"source":{"id":"https://openalex.org/S4306400906","display_name":"Research Repository (Delft University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98358874","host_organization_name":"Delft University of Technology","host_organization_lineage":["https://openalex.org/I98358874"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"thesis"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5600000023841858,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3193736345","https://openalex.org/W2768292657","https://openalex.org/W2165011274","https://openalex.org/W2745742916","https://openalex.org/W2278433511","https://openalex.org/W3092893053","https://openalex.org/W2903601652","https://openalex.org/W2243062237","https://openalex.org/W2884002000","https://openalex.org/W2963113198","https://openalex.org/W200780268","https://openalex.org/W2505513334","https://openalex.org/W2614457370","https://openalex.org/W2120335261","https://openalex.org/W3119632795","https://openalex.org/W3103838789","https://openalex.org/W2914219486","https://openalex.org/W2210176665","https://openalex.org/W2059382389","https://openalex.org/W2186514304"],"abstract_inverted_index":{"Though":[0],"field-programmable":[1],"gate":[2],"arrays":[3],"(FPGAs)":[4],"have":[5,13,24,56,124],"been":[6,15],"used":[7],"to":[8,26,52,114,157,208],"accelerate":[9,115],"database":[10,98,116,130,154,169],"systems,":[11],"they":[12],"not":[14],"widely":[16],"adopted":[17],"for":[18,151,192],"the":[19,35,68,97,120,129,135,179,182],"following":[20],"reasons.":[21],"As":[22],"databases":[23,193],"transitioned":[25],"higher":[27],"bandwidth":[28],"technology":[29,61,140],"such":[30],"as":[31,58,105,132,134],"in-memory":[32],"and":[33,54,76,110,178,205,218],"NVMe,":[34],"communication":[36],"overhead":[37],"associated":[38],"with":[39,62,67],"accelerators":[40,191],"has":[41],"become":[42],"more":[43,50],"of":[44,70,165,173,181,202,212],"a":[45,106,163,215,219],"burden.":[46],"Also,":[47],"FPGAs":[48,82,91,104,113,126,146],"are":[49,185],"difficult":[51],"program,":[53],"GPUs":[55],"emerged":[57],"an":[59,200],"alternative":[60],"better":[63],"programming":[64],"support.":[65],"However,":[66,156],"development":[69,180],"new":[71,168,171],"interconnect":[72],"technology,":[73,75],"memory":[74],"improved":[77],"FPGA":[78],"design":[79],"tool":[80,183],"chains,":[81],"again":[83,95],"provide":[84,148,199],"significant":[85,149],"opportunities.":[86],"Therefore,":[87],"we":[88],"believe":[89],"that":[90,123,145],"can":[92,147],"be":[93],"attractive":[94],"in":[96,128,153,162,195],"field.":[99],"This":[100],"thesis":[101],"focuses":[102],"on":[103,190],"high-performance":[107],"compute":[108],"platform,":[109],"explores":[111],"using":[112],"systems.":[117,155],"It":[118],"investigates":[119],"current":[121],"challenges":[122],"held":[125],"back":[127],"field":[131],"well":[133],"opportunities":[136],"resulting":[137],"from":[138],"recent":[139],"developments.":[141],"The":[142],"investigation":[143],"illustrates":[144],"advantages":[150],"integration":[152],"make":[158,206],"further":[159],"progress,":[160],"studies":[161],"number":[164],"areas,":[166],"including":[167],"architectures,":[170],"types":[172,211],"accelerators,":[174],"deep":[175],"performance":[176],"analysis,":[177],"chains":[184],"required.":[186],"Our":[187],"contributions":[188,207],"focus":[189],"implemented":[194],"reconfigurable":[196],"logic.":[197],"We":[198],"overview":[201],"prior":[203],"work":[204],"two":[209],"specific":[210],"accelerators:":[213],"both":[214],"compute-intensive":[216],"(decompression)":[217],"memory-intensive":[220],"(hash":[221],"join)":[222],"accelerator.":[223]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T06:51:31.235846","created_date":"2025-10-10T00:00:00"}