{"id":"https://openalex.org/W7134827430","doi":"https://doi.org/10.4230/oasics.ng-res.2026.3","title":"Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs","display_name":"Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7134827430","doi":"https://doi.org/10.4230/oasics.ng-res.2026.3"},"language":"en","primary_location":{"id":"pmh:oai:drops-oai.dagstuhl.de:25421","is_oa":true,"landing_page_url":"https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.3","pdf_url":"https://drops.dagstuhl.de/storage/01oasics/oasics-vol140-ng-res2026/OASIcs.NG-RES.2026.3/OASIcs.NG-RES.2026.3.pdf","source":{"id":"https://openalex.org/S4306402524","display_name":"Leibniz-Zentrum f\u00fcr Informatik (Schloss Dagstuhl)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2799853480","host_organization_name":"Schloss Dagstuhl \u2013 Leibniz Center for Informatics","host_organization_lineage":["https://openalex.org/I2799853480"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"publishedVersion"},"type":"article","indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://drops.dagstuhl.de/storage/01oasics/oasics-vol140-ng-res2026/OASIcs.NG-RES.2026.3/OASIcs.NG-RES.2026.3.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108930284","display_name":"K Asahina","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Asahina, Koki","raw_affiliation_strings":["Nara Institute of Science and Technology (NAIST), Ikoma, Japan"],"raw_orcid":"https://orcid.org/0009-0003-6155-7937","affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology (NAIST), Ikoma, Japan","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074853381","display_name":"Yasuhiko Nakashima","orcid":"https://orcid.org/0000-0002-9457-5061"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nakashima, Yasuhiko","raw_affiliation_strings":["Nara Institute of Science and Technology (NAIST), Ikoma, Japan"],"raw_orcid":"https://orcid.org/0000-0002-9457-5061","affiliations":[{"raw_affiliation_string":"Nara Institute of Science and Technology (NAIST), Ikoma, Japan","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108930284"],"corresponding_institution_ids":["https://openalex.org/I75917431"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.39297284,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0020000000949949026,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0010000000474974513,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5755000114440918},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5719000101089478},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4952999949455261},{"id":"https://openalex.org/keywords/greedy-algorithm","display_name":"Greedy algorithm","score":0.3718000054359436},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.3702999949455261},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.3686000108718872},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.3337000012397766}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7563999891281128},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5755000114440918},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5719000101089478},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4952999949455261},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48980000615119934},{"id":"https://openalex.org/C51823790","wikidata":"https://www.wikidata.org/wiki/Q504353","display_name":"Greedy algorithm","level":2,"score":0.3718000054359436},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.3702999949455261},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3686000108718872},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34929999709129333},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33730000257492065},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.3337000012397766},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.3319999873638153},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.3091999888420105},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.30660000443458557},{"id":"https://openalex.org/C128942645","wikidata":"https://www.wikidata.org/wiki/Q1568346","display_name":"Test case","level":3,"score":0.303600013256073},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.2759999930858612},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.25519999861717224},{"id":"https://openalex.org/C2777131613","wikidata":"https://www.wikidata.org/wiki/Q18394147","display_name":"Retard","level":2,"score":0.25220000743865967}],"mesh":[],"locations_count":3,"locations":[{"id":"pmh:oai:drops-oai.dagstuhl.de:25421","is_oa":true,"landing_page_url":"https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.3","pdf_url":"https://drops.dagstuhl.de/storage/01oasics/oasics-vol140-ng-res2026/OASIcs.NG-RES.2026.3/OASIcs.NG-RES.2026.3.pdf","source":{"id":"https://openalex.org/S4306402524","display_name":"Leibniz-Zentrum f\u00fcr Informatik (Schloss Dagstuhl)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2799853480","host_organization_name":"Schloss Dagstuhl \u2013 Leibniz Center for Informatics","host_organization_lineage":["https://openalex.org/I2799853480"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"publishedVersion"},{"id":"pmh:doi:10.4230/oasics.ng-res.2026.3","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"ConferencePaper"},{"id":"doi:10.4230/oasics.ng-res.2026.3","is_oa":true,"landing_page_url":"https://doi.org/10.4230/oasics.ng-res.2026.3","pdf_url":null,"source":{"id":"https://openalex.org/S7407052059","display_name":"Dagstuhl Research Online Publication Server","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":""}],"best_oa_location":{"id":"pmh:oai:drops-oai.dagstuhl.de:25421","is_oa":true,"landing_page_url":"https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.3","pdf_url":"https://drops.dagstuhl.de/storage/01oasics/oasics-vol140-ng-res2026/OASIcs.NG-RES.2026.3/OASIcs.NG-RES.2026.3.pdf","source":{"id":"https://openalex.org/S4306402524","display_name":"Leibniz-Zentrum f\u00fcr Informatik (Schloss Dagstuhl)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2799853480","host_organization_name":"Schloss Dagstuhl \u2013 Leibniz Center for Informatics","host_organization_lineage":["https://openalex.org/I2799853480"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"publishedVersion"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6253046989440918,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G6344380577","display_name":null,"funder_award_id":"JPMJAN23F4","funder_id":"https://openalex.org/F4320338115","funder_display_name":"Advanced Low Carbon Technology Research and Development Program"}],"funders":[{"id":"https://openalex.org/F4320338115","display_name":"Advanced Low Carbon Technology Research and Development Program","ror":null}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7134827430.pdf","grobid_xml":"https://content.openalex.org/works/W7134827430.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Memory":[0],"Built-In":[1],"Self-Test":[2],"(MBIST)":[3],"is":[4,146],"a":[5,76,102,109,119,212,244],"widely":[6],"adopted":[7],"technique":[8],"for":[9,51,64,236],"testing":[10],"memory.":[11],"In":[12,71,122],"modern":[13],"large-scale":[14,241],"SoCs,":[15],"hundreds":[16],"to":[17,25,85,132,148,199],"thousands":[18],"of":[19,94,163,195,249],"embedded":[20,250],"memories":[21,32],"are":[22,41,130],"integrated,":[23],"and":[24,33,91,108,127,141,160,186,233,247],"test":[26,34,52,86,116,152,219],"them":[27,35],"efficiently,":[28],"methods":[29],"that":[30,78,112,226],"group":[31,40],"in":[36,206,240],"parallel":[37],"within":[38],"each":[39],"employed.":[42],"However,":[43],"many":[44],"existing":[45,183],"approaches":[46],"either":[47],"do":[48],"not":[49],"account":[50],"scheduling":[53,110],"or":[54],"rely":[55],"on":[56,156,175],"evolutionary":[57],"methods,":[58,188],"such":[59],"as":[60],"genetic":[61],"algorithms":[62],"(GAs),":[63],"grouping,":[65],"which":[66],"incur":[67],"high":[68,231],"computational":[69],"costs.":[70],"this":[72],"work,":[73],"we":[74],"propose":[75],"framework":[77,100],"covers":[79],"the":[80,89,99,114,123,150,157,161,176,189,193,218,227],"flow":[81],"from":[82],"memory":[83,105],"grouping":[84,106,135],"scheduling.":[87],"Taking":[88],"specifications":[90],"layout":[92],"information":[93],"multiple":[95],"SRAMs":[96],"into":[97],"account,":[98],"comprises":[101],"flexible,":[103],"fast":[104,134],"method":[107,111,191,229],"minimizes":[113],"total":[115,151],"time":[117,153,220],"under":[118,154],"power-constrained":[120],"constraint.":[121],"proposed":[124,190,228],"approach,":[125],"DBSCAN":[126],"rectangular":[128],"partitioning":[129],"used":[131],"perform":[133],"while":[136,201],"suppressing":[137],"long":[138],"routing":[139],"connections,":[140],"an":[142],"LPT-based":[143],"greedy":[144],"heuristic":[145],"employed":[147],"shorten":[149],"constraints":[155],"power":[158],"limit":[159],"number":[162,194,246],"simultaneously":[164],"active":[165],"BIST":[166],"controllers.":[167],"Experimental":[168],"evaluation":[169],"using":[170],"SRAM":[171],"placement":[172],"data":[173],"based":[174],"ASAP7":[177],"PDK":[178],"shows":[179],"that,":[180],"compared":[181,210],"with":[182,211,243],"K-means,":[184],"Greedy,":[185],"GA-based":[187],"reduces":[192,217],"groups":[196],"by":[197,221],"up":[198],"48%":[200],"achieving":[202],"approximately":[203],"87\u00d7":[204],"speedup":[205],"clustering":[207],"runtime.":[208],"Furthermore,":[209],"commercial":[213],"Industrial":[214],"Solution,":[215],"it":[216],"53%.":[222],"These":[223],"results":[224],"demonstrate":[225],"provides":[230],"scalability":[232],"practical":[234],"effectiveness":[235],"MBIST":[237],"design,":[238],"even":[239],"MPSoCs":[242],"large":[245],"variety":[248],"memories.":[251]},"counts_by_year":[],"updated_date":"2026-03-11T06:17:14.884878","created_date":"2026-03-11T00:00:00"}