{"id":"https://openalex.org/W2074878180","doi":"https://doi.org/10.4018/jertcs.2012100103","title":"On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links","display_name":"On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2074878180","doi":"https://doi.org/10.4018/jertcs.2012100103","mag":"2074878180"},"language":"en","primary_location":{"id":"doi:10.4018/jertcs.2012100103","is_oa":false,"landing_page_url":"https://doi.org/10.4018/jertcs.2012100103","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050298468","display_name":"Sebastian H\u00f6ppner","orcid":"https://orcid.org/0000-0002-9938-2736"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian H\u00f6ppner","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091157874","display_name":"Dennis Walter","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dennis Walter","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059380044","display_name":"Georg Ellguth","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Georg Ellguth","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046407","display_name":"Ren\u00e9 Sch\u00fcffny","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ren\u00e9 Sch\u00fcffny","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.3631,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65036743,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"3","issue":"4","first_page":"42","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8251793384552002},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6655551195144653},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6521247625350952},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.590506911277771},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.5669174194335938},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4968426525592804},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.4504285454750061},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4301522672176361},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4129585027694702},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4120975732803345},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4066569209098816},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.376213937997818},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17495942115783691},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10203313827514648}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8251793384552002},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6655551195144653},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6521247625350952},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.590506911277771},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.5669174194335938},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4968426525592804},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.4504285454750061},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4301522672176361},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4129585027694702},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4120975732803345},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4066569209098816},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.376213937997818},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17495942115783691},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10203313827514648},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.4018/jertcs.2012100103","is_oa":false,"landing_page_url":"https://doi.org/10.4018/jertcs.2012100103","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"},{"id":"pmh:oai:RePEc:igg:jertcs:v:3:y:2012:i:4:p:42-56","is_oa":false,"landing_page_url":"http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jertcs.2012100103","pdf_url":null,"source":{"id":"https://openalex.org/S4306401271","display_name":"RePEc: Research Papers in Economics","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I77793887","host_organization_name":"Federal Reserve Bank of St. Louis","host_organization_lineage":["https://openalex.org/I77793887"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6000000238418579,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2025944889","https://openalex.org/W2046317813","https://openalex.org/W2073767541","https://openalex.org/W2094340265","https://openalex.org/W2098808037","https://openalex.org/W2103692532","https://openalex.org/W2125154572","https://openalex.org/W2145442218","https://openalex.org/W2157887705","https://openalex.org/W2550825926"],"related_works":["https://openalex.org/W1976012348","https://openalex.org/W2502691491","https://openalex.org/W4297990507","https://openalex.org/W2560375935","https://openalex.org/W2002682434","https://openalex.org/W2144357574","https://openalex.org/W1966325333","https://openalex.org/W3198758847","https://openalex.org/W3117657225","https://openalex.org/W4230458348"],"abstract_inverted_index":{"This":[0,33],"paper":[1],"presents":[2],"techniques":[3],"for":[4,47],"measurement":[5,65],"and":[6,13],"compensation":[7,81],"of":[8,16,30,37,60,82,101,118],"timing":[9],"variations":[10,84],"in":[11,104],"clock":[12,61],"data":[14],"channels":[15],"source-synchronous":[17],"high-speed":[18,87],"serial":[19],"network-on-chip":[20],"(NoC)":[21],"links.":[22,57],"Timing":[23],"mismatch":[24,70],"measurements":[25],"are":[26],"performed":[27],"by":[28,73],"means":[29],"asynchronous":[31],"sub-sampling.":[32],"allows":[34],"the":[35,64,113],"use":[36],"low":[38],"quality":[39],"sampling":[40],"clocks":[41],"to":[42,85],"reduce":[43],"test":[44],"hardware":[45],"overhead":[46],"integration":[48],"into":[49],"complex":[50],"MPSoCs":[51],"(Multiprocessor":[52],"System-on-Chip)":[53],"with":[54,90],"multiple":[55],"NoC":[56,88,97],"The":[58,77],"effect":[59],"jitter":[62],"on":[63],"results":[66],"is":[67,71,94],"evaluated.":[68],"Delay":[69],"compensated":[72],"tunable":[74],"delay":[75,83],"cells.":[76],"proposed":[78],"technique":[79],"enables":[80],"realize":[86],"links":[89,98],"sufficient":[91],"yield.":[92],"It":[93],"demonstrated":[95],"at":[96],"as":[99],"part":[100],"an":[102],"MPSoC":[103],"65":[105],"nm":[106],"Complementary":[107],"Metal":[108],"Oxide":[109],"Semiconductor":[110],"technology,":[111],"where":[112],"calibration":[114],"significantly":[115],"reduces":[116],"bit-error-rates":[117],"a":[119],"72":[120],"GBit/s":[121,123],"(8":[122],"per":[124],"lane)":[125],"link":[126],"over":[127],"4":[128],"mm":[129],"on-chip":[130],"interconnect.":[131]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T06:19:23.411458","created_date":"2025-10-10T00:00:00"}