{"id":"https://openalex.org/W1968018920","doi":"https://doi.org/10.4018/jertcs.2010070102","title":"Implementation of FFT on General-Purpose Architectures for FPGA","display_name":"Implementation of FFT on General-Purpose Architectures for FPGA","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W1968018920","doi":"https://doi.org/10.4018/jertcs.2010070102","mag":"1968018920"},"language":"en","primary_location":{"id":"doi:10.4018/jertcs.2010070102","is_oa":false,"landing_page_url":"https://doi.org/10.4018/jertcs.2010070102","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056978552","display_name":"Fabio Garzia","orcid":"https://orcid.org/0000-0003-2597-4429"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Fabio Garzia","raw_affiliation_strings":["Tampere University of Technology, Finland","Tampere University of Technology, , Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology, , Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049758849","display_name":"Roberto Airoldi","orcid":null},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Roberto Airoldi","raw_affiliation_strings":["Tampere University of Technology, Finland","Tampere University of Technology, , Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology, , Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Tampere University of Technology, Finland","Tampere University of Technology, , Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Tampere University of Technology, , Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06394052,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":"3","first_page":"24","last_page":"43"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.895972490310669},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7802932262420654},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5855842232704163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5494115948677063},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5263881683349609},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4894906282424927},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.47174251079559326},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.45035940408706665},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44826069474220276},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.44318971037864685},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.433838814496994},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3135755658149719}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.895972490310669},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7802932262420654},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5855842232704163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5494115948677063},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5263881683349609},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4894906282424927},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.47174251079559326},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.45035940408706665},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44826069474220276},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.44318971037864685},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.433838814496994},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3135755658149719},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.4018/jertcs.2010070102","is_oa":false,"landing_page_url":"https://doi.org/10.4018/jertcs.2010070102","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"},{"id":"pmh:oai:RePEc:igg:jertcs:v:1:y:2010:i:3:p:24-43","is_oa":false,"landing_page_url":"http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/jertcs.2010070102","pdf_url":null,"source":{"id":"https://openalex.org/S4306401271","display_name":"RePEc: Research Papers in Economics","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I77793887","host_organization_name":"Federal Reserve Bank of St. Louis","host_organization_lineage":["https://openalex.org/I77793887"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W7324480","https://openalex.org/W105298322","https://openalex.org/W1525385465","https://openalex.org/W1562922353","https://openalex.org/W1568614409","https://openalex.org/W1653106180","https://openalex.org/W2029292298","https://openalex.org/W2061171222","https://openalex.org/W2078561521","https://openalex.org/W2082280297","https://openalex.org/W2086135629","https://openalex.org/W2088028932","https://openalex.org/W2108249866","https://openalex.org/W2111046960","https://openalex.org/W2117099910","https://openalex.org/W2127373103","https://openalex.org/W2133712953","https://openalex.org/W2136864873","https://openalex.org/W2136888333","https://openalex.org/W2153630159","https://openalex.org/W2154646656","https://openalex.org/W2163442090","https://openalex.org/W2165499076","https://openalex.org/W4229693094","https://openalex.org/W4231896027"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W2113648965","https://openalex.org/W4200391368","https://openalex.org/W2155484023","https://openalex.org/W2388221044","https://openalex.org/W2619213283","https://openalex.org/W2984236338","https://openalex.org/W3117064361","https://openalex.org/W2057745131"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"two":[3,47,83],"general-purpose":[4,29],"architectures":[5,42],"targeted":[6],"to":[7,143],"Field":[8],"Programmable":[9],"Gate":[10],"Array":[11],"(FPGA)":[12],"implementation.":[13],"The":[14,32,76,96,119],"first":[15],"architecture":[16,34,127],"is":[17,35,98,113,139],"based":[18,115],"on":[19,81,116,128,158],"the":[20,60,67,70,82,101,105],"coupling":[21],"of":[22,69,78],"a":[23,28,36,52,55,79,86,92,125,135,140,145,150],"coarse-grain":[24],"reconfigurable":[25,102],"array":[26],"with":[27,91,149],"processor":[30],"core.":[31],"second":[33],"homogeneous":[37],"multi-processor":[38],"system-on-chip":[39],"(MP-SoC).":[40],"Both":[41],"have":[43],"been":[44],"mapped":[45],"onto":[46,59],"different":[48],"Altera":[49],"FPGA":[50,129],"devices,":[51],"StratixII":[53],"and":[54,130,155],"StratixIV.":[56],"Although":[57],"mapping":[58,156],"StratixIV":[61],"results":[62],"in":[63,89,100],"higher":[64,99],"operating":[65],"frequencies,":[66],"capabilities":[68],"device":[71],"are":[72],"not":[73],"fully":[74],"exploited.":[75],"implementation":[77],"FFT":[80],"platforms":[84],"shows":[85],"considerable":[87],"speed-up":[88,97],"comparison":[90],"single-processor":[93],"reference":[94],"architecture.":[95],"solution":[103],"but":[104],"MP-SoC":[106],"provides":[107],"an":[108],"easier":[109],"programming":[110,132],"interface":[111],"that":[112,123],"completely":[114],"C":[117],"language.":[118],"authors\u2019":[120],"approach":[121],"proves":[122],"implementing":[124],"programmable":[126],"then":[131],"it":[133,157],"using":[134],"high-level":[136],"software":[137],"language":[138,153],"viable":[141],"alternative":[142],"designing":[144],"dedicated":[146],"hardware":[147,151],"block":[148],"description":[152],"(HDL)":[154],"FPGA.":[159]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}