{"id":"https://openalex.org/W2922671868","doi":"https://doi.org/10.4018/ijertcs.2019040106","title":"Design of an Intelligent Data Cache with Replacement Policy","display_name":"Design of an Intelligent Data Cache with Replacement Policy","publication_year":2019,"publication_date":"2019-03-20","ids":{"openalex":"https://openalex.org/W2922671868","doi":"https://doi.org/10.4018/ijertcs.2019040106","mag":"2922671868"},"language":"en","primary_location":{"id":"doi:10.4018/ijertcs.2019040106","is_oa":false,"landing_page_url":"https://doi.org/10.4018/ijertcs.2019040106","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085637448","display_name":"B. Shameedha Begum","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"B. Shameedha Begum","raw_affiliation_strings":["National Institute of Technology Tiruchirappalli, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"National Institute of Technology Tiruchirappalli, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"last","author":{"id":null,"display_name":"N. Ramasubramanian","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"N. Ramasubramanian","raw_affiliation_strings":["National Institute of Technology Tiruchirappalli, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"National Institute of Technology Tiruchirappalli, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5085637448"],"corresponding_institution_ids":["https://openalex.org/I122964287"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02354132,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":"2","first_page":"87","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8742029666900635},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8558386564254761},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.78262859582901},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.6347445249557495},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5953322052955627},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5952878594398499},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.591168999671936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5695188045501709},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.43208563327789307},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42809027433395386},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42004308104515076},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.41411030292510986},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.319130539894104}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8742029666900635},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8558386564254761},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.78262859582901},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.6347445249557495},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5953322052955627},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5952878594398499},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.591168999671936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5695188045501709},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.43208563327789307},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42809027433395386},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42004308104515076},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.41411030292510986},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.319130539894104},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.4018/ijertcs.2019040106","is_oa":false,"landing_page_url":"https://doi.org/10.4018/ijertcs.2019040106","pdf_url":null,"source":{"id":"https://openalex.org/S172929737","display_name":"International Journal of Embedded and Real-Time Communication Systems","issn_l":"1947-3176","issn":["1947-3176","1947-3184"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320424","host_organization_name":"IGI Global","host_organization_lineage":["https://openalex.org/P4310320424"],"host_organization_lineage_names":["IGI Global"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded and Real-Time Communication Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W37085840","https://openalex.org/W1490422487","https://openalex.org/W1555915743","https://openalex.org/W1883923933","https://openalex.org/W1973873209","https://openalex.org/W1986465830","https://openalex.org/W2024447080","https://openalex.org/W2032687317","https://openalex.org/W2043512019","https://openalex.org/W2055166015","https://openalex.org/W2063389777","https://openalex.org/W2074088899","https://openalex.org/W2086802227","https://openalex.org/W2100447702","https://openalex.org/W2109077597","https://openalex.org/W2111417401","https://openalex.org/W2132366470","https://openalex.org/W2149590159","https://openalex.org/W2150938982","https://openalex.org/W2153456949","https://openalex.org/W2156506280","https://openalex.org/W2159240786","https://openalex.org/W2162687094","https://openalex.org/W2164157607","https://openalex.org/W2240016677","https://openalex.org/W3004935110","https://openalex.org/W3005036649","https://openalex.org/W3015385986","https://openalex.org/W4235185265","https://openalex.org/W6675054392"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2363769136","https://openalex.org/W2114386333","https://openalex.org/W2126408955","https://openalex.org/W2539712666","https://openalex.org/W2148571123","https://openalex.org/W2396934146","https://openalex.org/W2369103246","https://openalex.org/W2734782074","https://openalex.org/W2115222420"],"abstract_inverted_index":{"Embedded":[0],"systems":[1],"are":[2],"designed":[3],"for":[4,25,61,104,137],"a":[5,68,72,89],"variety":[6],"of":[7,22,38,71,145],"applications":[8,14,30,139],"ranging":[9],"from":[10],"Hard":[11],"Real":[12],"Time":[13],"to":[15,56,129,135],"mobile":[16],"computing,":[17],"which":[18,140],"demands":[19],"various":[20],"types":[21],"cache":[23,40,63,77,87,95,105,112],"designs":[24],"better":[26],"performance.":[27,64,106],"Since":[28],"real-time":[29],"place":[31],"stringent":[32],"requirements":[33,48],"on":[34,80],"performance,":[35],"the":[36,39,111,121],"role":[37],"subsystem":[41],"assumes":[42],"significance.":[43],"Reconfigurable":[44],"caches":[45,54],"meet":[46],"performance":[47,144],"under":[49],"this":[50],"context.":[51],"Existing":[52],"reconfigurable":[53,73,91],"tend":[55],"use":[57],"associativity":[58],"and":[59,74,88,102,131],"size":[60],"maximizing":[62],"This":[65],"article":[66],"proposes":[67],"novel":[69],"approach":[70],"intelligent":[75,84,92],"data":[76,86,94],"(L1)":[78],"based":[79],"replacement":[81,116],"algorithms.":[82],"An":[83],"embedded":[85,93,146],"dynamic":[90],"have":[96,118],"been":[97],"implemented":[98],"using":[99],"Verilog":[100],"2001":[101],"tested":[103],"Data":[107],"collected":[108],"by":[109,125],"enabling":[110],"with":[113],"two":[114],"different":[115],"strategies":[117],"shown":[119],"that":[120],"hit":[122],"rate":[123],"improves":[124],"40%":[126],"when":[127,133],"compared":[128,134],"LRU":[130],"21%":[132],"MRU":[136],"sequential":[138],"will":[141],"significantly":[142],"improve":[143],"real":[147],"time":[148],"application.":[149]},"counts_by_year":[],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
