{"id":"https://openalex.org/W4380987008","doi":"https://doi.org/10.3390/sym15061272","title":"From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits","display_name":"From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits","publication_year":2023,"publication_date":"2023-06-16","ids":{"openalex":"https://openalex.org/W4380987008","doi":"https://doi.org/10.3390/sym15061272"},"language":"en","primary_location":{"id":"doi:10.3390/sym15061272","is_oa":true,"landing_page_url":"https://doi.org/10.3390/sym15061272","pdf_url":"https://www.mdpi.com/2073-8994/15/6/1272/pdf?version=1687155648","source":{"id":"https://openalex.org/S190787756","display_name":"Symmetry","issn_l":"2073-8994","issn":["2073-8994"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Symmetry","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://www.mdpi.com/2073-8994/15/6/1272/pdf?version=1687155648","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062522781","display_name":"Yi-Ding Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiding Wei","raw_affiliation_strings":["Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100361964","display_name":"Jun Liu","orcid":"https://orcid.org/0000-0002-8627-5085"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jun Liu","raw_affiliation_strings":["Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037059696","display_name":"Dengbao Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dengbao Sun","raw_affiliation_strings":["Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084150655","display_name":"Guodong Su","orcid":"https://orcid.org/0000-0001-6927-9183"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guodong Su","raw_affiliation_strings":["Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"],"raw_orcid":"https://orcid.org/0000-0001-6927-9183","affiliations":[{"raw_affiliation_string":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020902466","display_name":"Junchao Wang","orcid":"https://orcid.org/0000-0002-6749-1858"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junchao Wang","raw_affiliation_strings":["Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China","institution_ids":["https://openalex.org/I50760025"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5100361964"],"corresponding_institution_ids":["https://openalex.org/I50760025"],"apc_list":{"value":2000,"currency":"CHF","value_usd":2227},"apc_paid":{"value":2000,"currency":"CHF","value_usd":2227},"fwci":0.4134,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.53008421,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"15","issue":"6","first_page":"1272","last_page":"1272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rfic","display_name":"RFIC","score":0.856329083442688},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6561241745948792},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6179870963096619},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4903566837310791},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4755237400531769},{"id":"https://openalex.org/keywords/image-stitching","display_name":"Image stitching","score":0.4728391766548157},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.47189459204673767},{"id":"https://openalex.org/keywords/repeater","display_name":"Repeater (horology)","score":0.4601166546344757},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.437934547662735},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.432053804397583},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4312363266944885},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.4198707342147827},{"id":"https://openalex.org/keywords/radio-frequency","display_name":"Radio frequency","score":0.3791022300720215},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3766217827796936},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.3655659556388855},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29886192083358765},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2589426040649414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21628007292747498},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.20897945761680603},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1810712218284607},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.1512584388256073},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13705125451087952}],"concepts":[{"id":"https://openalex.org/C121152627","wikidata":"https://www.wikidata.org/wiki/Q6095735","display_name":"RFIC","level":3,"score":0.856329083442688},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6561241745948792},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6179870963096619},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4903566837310791},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4755237400531769},{"id":"https://openalex.org/C29081049","wikidata":"https://www.wikidata.org/wiki/Q1364242","display_name":"Image stitching","level":2,"score":0.4728391766548157},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.47189459204673767},{"id":"https://openalex.org/C195545963","wikidata":"https://www.wikidata.org/wiki/Q1469803","display_name":"Repeater (horology)","level":3,"score":0.4601166546344757},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.437934547662735},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.432053804397583},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4312363266944885},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.4198707342147827},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.3791022300720215},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3766217827796936},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3655659556388855},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29886192083358765},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2589426040649414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21628007292747498},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.20897945761680603},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1810712218284607},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.1512584388256073},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13705125451087952},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.3390/sym15061272","is_oa":true,"landing_page_url":"https://doi.org/10.3390/sym15061272","pdf_url":"https://www.mdpi.com/2073-8994/15/6/1272/pdf?version=1687155648","source":{"id":"https://openalex.org/S190787756","display_name":"Symmetry","issn_l":"2073-8994","issn":["2073-8994"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Symmetry","raw_type":"journal-article"},{"id":"pmh:oai:mdpi.com:/2073-8994/15/6/1272/","is_oa":true,"landing_page_url":"https://dx.doi.org/10.3390/sym15061272","pdf_url":"https://dx.doi.org/10.3390/sym15061272","source":{"id":"https://openalex.org/S4306400947","display_name":"MDPI (MDPI AG)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210097602","host_organization_name":"Multidisciplinary Digital Publishing Institute (Switzerland)","host_organization_lineage":["https://openalex.org/I4210097602"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Symmetry; Volume 15; Issue 6; Pages: 1272","raw_type":"Text"},{"id":"pmh:oai:doaj.org/article:9c2bee22172f43959286811aee699bac","is_oa":false,"landing_page_url":"https://doaj.org/article/9c2bee22172f43959286811aee699bac","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Symmetry, Vol 15, Iss 6, p 1272 (2023)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.3390/sym15061272","is_oa":true,"landing_page_url":"https://doi.org/10.3390/sym15061272","pdf_url":"https://www.mdpi.com/2073-8994/15/6/1272/pdf?version=1687155648","source":{"id":"https://openalex.org/S190787756","display_name":"Symmetry","issn_l":"2073-8994","issn":["2073-8994"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Symmetry","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4380987008.pdf","grobid_xml":"https://content.openalex.org/works/W4380987008.grobid-xml"},"referenced_works_count":28,"referenced_works":["https://openalex.org/W2007959382","https://openalex.org/W2019159402","https://openalex.org/W2052897097","https://openalex.org/W2054057704","https://openalex.org/W2062528358","https://openalex.org/W2088586905","https://openalex.org/W2113801595","https://openalex.org/W2144743394","https://openalex.org/W2155826944","https://openalex.org/W2171049754","https://openalex.org/W2176172550","https://openalex.org/W2184714462","https://openalex.org/W2500309851","https://openalex.org/W2543058359","https://openalex.org/W2583707817","https://openalex.org/W2922312776","https://openalex.org/W2963542386","https://openalex.org/W2968704754","https://openalex.org/W2998080880","https://openalex.org/W3098335909","https://openalex.org/W3171752851","https://openalex.org/W4200516030","https://openalex.org/W4214645104","https://openalex.org/W4223500862","https://openalex.org/W4283819034","https://openalex.org/W4297337240","https://openalex.org/W4310173407","https://openalex.org/W6676006044"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W1605062719","https://openalex.org/W2376028644","https://openalex.org/W2044122268","https://openalex.org/W2162651506","https://openalex.org/W1565715208","https://openalex.org/W1964352816","https://openalex.org/W2102933388","https://openalex.org/W2583707817","https://openalex.org/W2304374807"],"abstract_inverted_index":{"Layout":[0],"stitching":[1,112],"is":[2,32],"a":[3,34,46,136],"repetitive":[4],"and":[5,28,52,101,135],"tedious":[6],"task":[7],"of":[8,36,77,99],"the":[9,75,82,88,96,124],"radio":[10],"frequency":[11],"integrated":[12],"circuit":[13,91,106],"(RFIC)":[14],"design":[15],"process.":[16],"While":[17],"academic":[18],"research":[19],"on":[20,26,81,87,105,132],"layout":[21,76],"splicing":[22,103],"algorithms":[23,38],"mainly":[24],"focuses":[25],"analog":[27],"digital":[29],"circuits,":[30],"there":[31],"still":[33],"lack":[35],"well-developed":[37],"for":[39,74],"RFICs.":[40],"An":[41],"RFIC":[42],"system":[43],"usually":[44],"has":[45],"symmetrical":[47],"layout,":[48],"such":[49],"as":[50],"transmitter":[51],"receiver":[53],"components,":[54],"low-noise":[55],"amplifier":[56],"(LNA),":[57],"an":[58,71,133],"SPDT":[59],"switch,":[60],"etc.":[61],"This":[62,93],"paper":[63],"aims":[64],"to":[65],"address":[66],"this":[67],"gap":[68],"by":[69,79],"proposing":[70],"automated":[72],"procedure":[73],"RFICs":[78],"relying":[80],"basic":[83],"device/PCell":[84],"structure":[85],"based":[86,104],"interconnection":[89],"among":[90],"topologies.":[92],"approach":[94],"makes":[95],"in-series":[97],"generation":[98],"layouts":[100],"automatic":[102],"logic":[107],"possible,":[108],"resulting":[109],"in":[110,118],"superior":[111],"performance":[113],"compared":[114],"with":[115],"related":[116],"modules":[117],"Advanced":[119],"Design":[120],"System.":[121],"To":[122],"demonstrate":[123],"physical":[125],"application":[126],"possibilities,":[127],"we":[128],"implemented":[129],"our":[130],"algorithm":[131],"LNA":[134],"switch":[137],"circuit.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-08-04T08:18:43.703281","created_date":"2023-06-17T00:00:00"}
