{"id":"https://openalex.org/W2539284540","doi":"https://doi.org/10.3390/computation4040041","title":"Evaluation of External Memory Access Performance on a High-End FPGA Hybrid Computer","display_name":"Evaluation of External Memory Access Performance on a High-End FPGA Hybrid Computer","publication_year":2016,"publication_date":"2016-10-25","ids":{"openalex":"https://openalex.org/W2539284540","doi":"https://doi.org/10.3390/computation4040041","mag":"2539284540"},"language":"en","primary_location":{"id":"doi:10.3390/computation4040041","is_oa":true,"landing_page_url":"https://doi.org/10.3390/computation4040041","pdf_url":"https://www.mdpi.com/2079-3197/4/4/41/pdf?version=1477364426","source":{"id":"https://openalex.org/S2738402919","display_name":"Computation","issn_l":"2079-3197","issn":["2079-3197"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computation","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://www.mdpi.com/2079-3197/4/4/41/pdf?version=1477364426","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053860740","display_name":"Konstantinos Kalaitzis","orcid":null},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Konstantinos Kalaitzis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece","institution_ids":["https://openalex.org/I55741626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042566983","display_name":"Evripidis Sotiriadis","orcid":null},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Evripidis Sotiriadis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece","institution_ids":["https://openalex.org/I55741626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032739499","display_name":"Ioannis Papaefstathiou","orcid":"https://orcid.org/0000-0001-6386-5616"},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Ioannis Papaefstathiou","raw_affiliation_strings":["School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece","institution_ids":["https://openalex.org/I55741626"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056983242","display_name":"Apostolos Dollas","orcid":null},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Apostolos Dollas","raw_affiliation_strings":["School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Technical University of Crete, Chania 731 00, Greece","institution_ids":["https://openalex.org/I55741626"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5056983242"],"corresponding_institution_ids":["https://openalex.org/I55741626"],"apc_list":{"value":1400,"currency":"CHF","value_usd":1515},"apc_paid":{"value":1400,"currency":"CHF","value_usd":1515},"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12157341,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":"4","first_page":"41","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.831082820892334},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.7644749283790588},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.691163182258606},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6846938729286194},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.585909366607666},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.5678350329399109},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5527884364128113},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5517999529838562},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.48168739676475525},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.46519267559051514},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.45729362964630127},{"id":"https://openalex.org/keywords/auxiliary-memory","display_name":"Auxiliary memory","score":0.4281068444252014},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4259442687034607},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4155125021934509},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37618616223335266},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.36227309703826904}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.831082820892334},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.7644749283790588},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.691163182258606},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6846938729286194},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.585909366607666},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.5678350329399109},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5527884364128113},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5517999529838562},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.48168739676475525},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.46519267559051514},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.45729362964630127},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.4281068444252014},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4259442687034607},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4155125021934509},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37618616223335266},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.36227309703826904}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.3390/computation4040041","is_oa":true,"landing_page_url":"https://doi.org/10.3390/computation4040041","pdf_url":"https://www.mdpi.com/2079-3197/4/4/41/pdf?version=1477364426","source":{"id":"https://openalex.org/S2738402919","display_name":"Computation","issn_l":"2079-3197","issn":["2079-3197"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computation","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:c22bd7659f4f4c9494924a8f065def1e","is_oa":true,"landing_page_url":"https://doaj.org/article/c22bd7659f4f4c9494924a8f065def1e","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Computation, Vol 4, Iss 4, p 41 (2016)","raw_type":"article"},{"id":"pmh:oai:mdpi.com:/2079-3197/4/4/41/","is_oa":true,"landing_page_url":"https://dx.doi.org/10.3390/computation4040041","pdf_url":null,"source":{"id":"https://openalex.org/S4306400947","display_name":"MDPI (MDPI AG)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210097602","host_organization_name":"Multidisciplinary Digital Publishing Institute (Switzerland)","host_organization_lineage":["https://openalex.org/I4210097602"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Computation; Volume 4; Issue 4; Pages: 41","raw_type":"Text"}],"best_oa_location":{"id":"doi:10.3390/computation4040041","is_oa":true,"landing_page_url":"https://doi.org/10.3390/computation4040041","pdf_url":"https://www.mdpi.com/2079-3197/4/4/41/pdf?version=1477364426","source":{"id":"https://openalex.org/S2738402919","display_name":"Computation","issn_l":"2079-3197","issn":["2079-3197"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310310987","host_organization_name":"Multidisciplinary Digital Publishing Institute","host_organization_lineage":["https://openalex.org/P4310310987"],"host_organization_lineage_names":["Multidisciplinary Digital Publishing Institute"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computation","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[{"id":"https://openalex.org/G2662765985","display_name":null,"funder_award_id":"H2020","funder_id":"https://openalex.org/F4320321917","funder_display_name":"General Secretariat for Research and Technology"},{"id":"https://openalex.org/G7331901853","display_name":null,"funder_award_id":"EU H2020","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320321917","display_name":"General Secretariat for Research and Technology","ror":"https://ror.org/04yeh8h63"},{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2539284540.pdf","grobid_xml":"https://content.openalex.org/works/W2539284540.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W183237244","https://openalex.org/W2025763720","https://openalex.org/W2040412852","https://openalex.org/W2058733701","https://openalex.org/W2096280516","https://openalex.org/W2113921339","https://openalex.org/W2183528605","https://openalex.org/W2284104857","https://openalex.org/W6607458128"],"related_works":["https://openalex.org/W2491097902","https://openalex.org/W4243333834","https://openalex.org/W4312264564","https://openalex.org/W1554378476","https://openalex.org/W4379620206","https://openalex.org/W2057195881","https://openalex.org/W2062140197","https://openalex.org/W4232365528","https://openalex.org/W2133063415","https://openalex.org/W2072931004"],"abstract_inverted_index":{"The":[0,45,62,95,152,186,206],"motivation":[1],"of":[2,12,48,51,59,65,105,114,145,155,174,177,183,188,208,246],"this":[3,165,189,222],"research":[4],"was":[5,132],"to":[6,84,121,127,147,163,192,237,242],"evaluate":[7],"the":[8,19,25,49,52,57,66,86,89,92,101,106,123,138,156,160,175,181,209,214,227,238],"main":[9],"memory":[10,34,37,50,67,93,107,169,178,204,215,228],"performance":[11],"a":[13,143,172],"hybrid":[14],"super":[15],"computer":[16],"such":[17],"as":[18,171],"Convey":[20,53,139,157],"HC-x,":[21],"and":[22,91,180,217,248],"ascertain":[23],"how":[24,213],"controller":[26],"performs":[27],"in":[28,42,119,137,159,194,254],"several":[29],"access":[30,103,128],"scenarios,":[31],"vis-\u00e0-vis":[32],"hand-coded":[33,203],"prefetches.":[35],"Such":[36],"patterns":[38],"are":[39,76],"very":[40],"useful":[41,71],"stencil":[43],"computations.":[44],"theoretical":[46],"bandwidth":[47,87],"is":[54,69,251],"compared":[55],"with":[56,202],"results":[58,211],"our":[60],"measurements.":[61],"accurate":[63],"study":[64],"subsystem":[68,216],"particularly":[70],"for":[72,134],"users":[73],"when":[74],"they":[75,240],"developing":[77],"their":[78],"application-specific":[79],"personality.":[80],"Experiments":[81],"were":[82,117],"performed":[83,200],"measure":[85,168],"between":[88],"coprocessor":[90,161],"subsystem.":[94],"experiments":[96,201],"aimed":[97],"mainly":[98],"at":[99],"measuring":[100],"reading":[102],"speed":[104],"from":[108],"Application":[109],"Engines":[110],"(FPGAs).":[111],"Different":[112],"ways":[113],"accessing":[115],"data":[116],"used":[118],"order":[120],"find":[122],"most":[124,195,255],"efficient":[125],"way":[126,131],"memory.":[129],"This":[130],"proposed":[133],"future":[135],"work":[136,223],"HC-x.":[140],"When":[141],"performing":[142],"series":[144],"accesses":[146,179],"memory,":[148],"non-uniform":[149],"latencies":[150],"occur.":[151],"Memory":[153,218],"Controller":[154],"HC-x":[158],"attempts":[162],"cover":[164],"latency.":[166],"We":[167],"efficiency":[170],"ratio":[173],"number":[176,182],"execution":[184],"cycles.":[185],"result":[187],"measurement":[190],"converges":[191],"one":[193],"cases.":[196],"In":[197],"addition,":[198],"we":[199,224],"accesses.":[205],"analysis":[207],"experimental":[210],"shows":[212],"Controllers":[219],"work.":[220],"From":[221],"conclude":[225],"that":[226],"controllers":[229],"do":[230],"an":[231],"excellent":[232],"job,":[233],"largely":[234],"because":[235],"(transparently":[236],"user)":[239],"seem":[241],"cache":[243],"large":[244],"amounts":[245],"data,":[247],"hence":[249],"hand-coding":[250],"not":[252],"needed":[253],"situations.":[256]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}