{"id":"https://openalex.org/W2925798220","doi":"https://doi.org/10.3233/jifs-169981","title":"Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm","display_name":"Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm","publication_year":2019,"publication_date":"2019-03-28","ids":{"openalex":"https://openalex.org/W2925798220","doi":"https://doi.org/10.3233/jifs-169981","mag":"2925798220"},"language":"en","primary_location":{"id":"doi:10.3233/jifs-169981","is_oa":false,"landing_page_url":"https://doi.org/10.3233/jifs-169981","pdf_url":null,"source":{"id":"https://openalex.org/S179157397","display_name":"Journal of Intelligent & Fuzzy Systems","issn_l":"1064-1246","issn":["1064-1246","1875-8967"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318577","host_organization_name":"IOS Press","host_organization_lineage":["https://openalex.org/P4310318577"],"host_organization_lineage_names":["IOS Press"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Intelligent &amp; Fuzzy Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Sasikumar Asaithambi","orcid":null},"institutions":[{"id":"https://openalex.org/I932239252","display_name":"SASTRA University","ror":"https://ror.org/032jk8892","country_code":"IN","type":"education","lineage":["https://openalex.org/I932239252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sasikumar Asaithambi","raw_affiliation_strings":["School of Computing, SASTRA Deemed University, Thanjavur, India"],"affiliations":[{"raw_affiliation_string":"School of Computing, SASTRA Deemed University, Thanjavur, India","institution_ids":["https://openalex.org/I932239252"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Muthaiah Rajappa","orcid":null},"institutions":[{"id":"https://openalex.org/I932239252","display_name":"SASTRA University","ror":"https://ror.org/032jk8892","country_code":"IN","type":"education","lineage":["https://openalex.org/I932239252"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Muthaiah Rajappa","raw_affiliation_strings":["School of Computing, SASTRA Deemed University, Thanjavur, India"],"affiliations":[{"raw_affiliation_string":"School of Computing, SASTRA Deemed University, Thanjavur, India","institution_ids":["https://openalex.org/I932239252"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036334864","display_name":"Logesh Ravi","orcid":"https://orcid.org/0000-0002-0034-4714"},"institutions":[{"id":"https://openalex.org/I932239252","display_name":"SASTRA University","ror":"https://ror.org/032jk8892","country_code":"IN","type":"education","lineage":["https://openalex.org/I932239252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Logesh Ravi","raw_affiliation_strings":["School of Computing, SASTRA Deemed University, Thanjavur, India"],"affiliations":[{"raw_affiliation_string":"School of Computing, SASTRA Deemed University, Thanjavur, India","institution_ids":["https://openalex.org/I932239252"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I932239252"],"apc_list":null,"apc_paid":null,"fwci":0.4842,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.64548132,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"36","issue":"5","first_page":"4235","last_page":"4245"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6261507272720337},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6211535930633545},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6106153726577759},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5299922823905945},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5057659149169922},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4885488450527191},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.4789465069770813},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46930578351020813},{"id":"https://openalex.org/keywords/particle-swarm-optimization","display_name":"Particle swarm optimization","score":0.41037800908088684},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27816241979599},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24288487434387207},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23729932308197021}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6261507272720337},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6211535930633545},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6106153726577759},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5299922823905945},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5057659149169922},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4885488450527191},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.4789465069770813},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46930578351020813},{"id":"https://openalex.org/C85617194","wikidata":"https://www.wikidata.org/wiki/Q2072794","display_name":"Particle swarm optimization","level":2,"score":0.41037800908088684},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27816241979599},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24288487434387207},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23729932308197021},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.3233/jifs-169981","is_oa":false,"landing_page_url":"https://doi.org/10.3233/jifs-169981","pdf_url":null,"source":{"id":"https://openalex.org/S179157397","display_name":"Journal of Intelligent & Fuzzy Systems","issn_l":"1064-1246","issn":["1064-1246","1875-8967"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318577","host_organization_name":"IOS Press","host_organization_lineage":["https://openalex.org/P4310318577"],"host_organization_lineage_names":["IOS Press"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Intelligent &amp; Fuzzy Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320325852","display_name":"SASTRA University","ror":"https://ror.org/032jk8892"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1536945048","https://openalex.org/W1594120130","https://openalex.org/W1979476900","https://openalex.org/W1994218207","https://openalex.org/W1996586364","https://openalex.org/W1999357165","https://openalex.org/W2027986690","https://openalex.org/W2038669746","https://openalex.org/W2039300364","https://openalex.org/W2061438946","https://openalex.org/W2061583850","https://openalex.org/W2065183815","https://openalex.org/W2067964949","https://openalex.org/W2075499381","https://openalex.org/W2075867689","https://openalex.org/W2082263180","https://openalex.org/W2095157116","https://openalex.org/W2100128641","https://openalex.org/W2106476087","https://openalex.org/W2109799889","https://openalex.org/W2112667233","https://openalex.org/W2120889849","https://openalex.org/W2137755681","https://openalex.org/W2141776905","https://openalex.org/W2144133630","https://openalex.org/W2147849504","https://openalex.org/W2155747840","https://openalex.org/W2171074980","https://openalex.org/W2295972482","https://openalex.org/W2621325273","https://openalex.org/W2736872590","https://openalex.org/W2754948887","https://openalex.org/W2772032055","https://openalex.org/W2789374566","https://openalex.org/W2794058155","https://openalex.org/W4243066171","https://openalex.org/W4243099375","https://openalex.org/W4249049401","https://openalex.org/W4249517230"],"related_works":["https://openalex.org/W2499505660","https://openalex.org/W2167327848","https://openalex.org/W3037468513","https://openalex.org/W4244211680","https://openalex.org/W2561828749","https://openalex.org/W3166315890","https://openalex.org/W4249015575","https://openalex.org/W2120134802","https://openalex.org/W2182902953","https://openalex.org/W4318953393"],"abstract_inverted_index":{"Guaranteeing":[0],"the":[1,18,23,34,42,60,88,93,102,118,129,140,144],"reliability":[2],"of":[3,50,92,117],"cyber-physical":[4],"systems":[5],"(CPS)":[6],"requires":[7],"analog":[8],"integrated":[9,15],"circuits":[10,16],"for":[11,25,40,74,113,147],"correct":[12],"functioning.":[13],"Analog":[14],"capture":[17],"continuous":[19],"signal":[20,24],"and":[21,46,54,81,105,160],"amplify":[22],"further":[26],"processing":[27],"in":[28],"CPS":[29],"applications.":[30],"This":[31],"paper":[32],"presents":[33],"hybrid":[35,69,110],"swarm":[36],"intelligence":[37],"based":[38,63],"approach":[39],"determining":[41],"optimal":[43,115],"transistors":[44],"sizes":[45],"bias":[47,106],"current":[48,107],"values":[49,108],"CMOS":[51,119,121],"differential":[52],"amplifier":[53],"an":[55,114],"operational":[56],"amplifier.":[57],"We":[58],"proposed":[59,133,141],"simplex":[61],"search":[62,90],"global":[64],"optimization":[65,72,94,134],"method":[66,142],"called":[67],"a":[68],"grey":[70],"wolf":[71],"(GWO)":[73],"solving":[75],"amplifiers":[76],"circuit":[77,130,148],"sizing":[78],"problems.":[79],"Simplex":[80],"GWO":[82,111],"techniques":[83],"were":[84],"combined":[85],"to":[86,100,127],"improve":[87],"local":[89],"capabilities":[91],"method.":[95],"Our":[96],"main":[97],"aim":[98],"is":[99],"optimize":[101],"transistor":[103],"size":[104],"using":[109,132],"algorithm":[112],"design":[116],"amplifiers.":[120],"180":[122],"nm":[123],"technology":[124],"was":[125],"utilized":[126],"finding":[128],"performance":[131,149],"approach.":[135],"Simulation":[136],"result":[137,146],"shows":[138],"that":[139],"provides":[143],"better":[145],"parameters":[150],"such":[151],"as":[152],"DC":[153],"gain,":[154],"phase":[155],"margin,":[156],"unity":[157],"gain":[158],"bandwidth":[159],"power":[161],"dissipation.":[162]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
