{"id":"https://openalex.org/W106358838","doi":"https://doi.org/10.3233/ica-2000-7104","title":"Implementing fine grain processor arrays on field-programmable logic","display_name":"Implementing fine grain processor arrays on field-programmable logic","publication_year":2000,"publication_date":"2000-01-01","ids":{"openalex":"https://openalex.org/W106358838","doi":"https://doi.org/10.3233/ica-2000-7104","mag":"106358838"},"language":"en","primary_location":{"id":"doi:10.3233/ica-2000-7104","is_oa":false,"landing_page_url":"https://doi.org/10.3233/ica-2000-7104","pdf_url":null,"source":{"id":"https://openalex.org/S107631664","display_name":"Integrated Computer-Aided Engineering","issn_l":"1069-2509","issn":["1069-2509","1875-8835"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318577","host_organization_name":"IOS Press","host_organization_lineage":["https://openalex.org/P4310318577"],"host_organization_lineage_names":["IOS Press"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integrated Computer-Aided Engineering","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069500732","display_name":"Istv\u00e1n Vass\u00e1nyi","orcid":"https://orcid.org/0000-0002-9833-8864"},"institutions":[{"id":"https://openalex.org/I140275651","display_name":"University of Pannonia","ror":"https://ror.org/03y5egs41","country_code":"HU","type":"education","lineage":["https://openalex.org/I140275651"]},{"id":"https://openalex.org/I4210127496","display_name":"Veszpr\u00e9mi \u00c9rseki Hittudom\u00e1nyi F\u00f5iskola","ror":"https://ror.org/03js41c71","country_code":"HU","type":"education","lineage":["https://openalex.org/I4210127496"]}],"countries":["HU"],"is_corresponding":true,"raw_author_name":"I. Vass\u00e1nyi","raw_affiliation_strings":["Department of Information Systems, University of Veszpr\u00e9m, H-8200 Veszpr\u00e9m, Hungary. E-mail: vassanyi@irt.vein.hu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Systems, University of Veszpr\u00e9m, H-8200 Veszpr\u00e9m, Hungary. E-mail: vassanyi@irt.vein.hu","institution_ids":["https://openalex.org/I4210127496","https://openalex.org/I140275651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5069500732"],"corresponding_institution_ids":["https://openalex.org/I140275651","https://openalex.org/I4210127496"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00699808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"1","first_page":"53","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5082747340202332},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.44074639678001404},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4397917687892914},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3644861578941345},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3275607228279114},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32276463508605957},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10213202238082886}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5082747340202332},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.44074639678001404},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4397917687892914},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3644861578941345},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3275607228279114},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32276463508605957},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10213202238082886},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.3233/ica-2000-7104","is_oa":false,"landing_page_url":"https://doi.org/10.3233/ica-2000-7104","pdf_url":null,"source":{"id":"https://openalex.org/S107631664","display_name":"Integrated Computer-Aided Engineering","issn_l":"1069-2509","issn":["1069-2509","1875-8835"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310318577","host_organization_name":"IOS Press","host_organization_lineage":["https://openalex.org/P4310318577"],"host_organization_lineage_names":["IOS Press"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integrated Computer-Aided Engineering","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W6377624","https://openalex.org/W1505235019","https://openalex.org/W1526973469","https://openalex.org/W1542864593","https://openalex.org/W1564419782","https://openalex.org/W1595386948","https://openalex.org/W1634309872","https://openalex.org/W1941202086","https://openalex.org/W1969116522","https://openalex.org/W2064688365","https://openalex.org/W2097333386","https://openalex.org/W2098243659","https://openalex.org/W2101942187","https://openalex.org/W2142299417","https://openalex.org/W2158901487","https://openalex.org/W2164890169","https://openalex.org/W2263452264","https://openalex.org/W2995746888"],"related_works":["https://openalex.org/W3033106587","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2160474882","https://openalex.org/W3209249181","https://openalex.org/W2009614483","https://openalex.org/W1563427385","https://openalex.org/W938986225","https://openalex.org/W2238679425","https://openalex.org/W1608572506"],"abstract_inverted_index":{"The":[0,16],"structure":[1],"of":[2,11,25],"Field":[3],"Programmable":[4],"Gate":[5],"Arrays":[6],"(FPGAs)":[7],"naturally":[8],"fits":[9],"that":[10],"fine":[12],"grain":[13],"array":[14],"algorithms.":[15],"paper":[17],"investigates":[18],"the":[19],"geometrical":[20],"and":[21],"layout-related":[22],"implementation":[23],"problems":[24],"FPGA-based":[26],"processor":[27],"arrays.":[28],"A":[29],"general":[30],"methodology":[31],"for":[32],"im":[33]},"counts_by_year":[],"updated_date":"2026-05-03T06:03:33.228499","created_date":"2025-10-10T00:00:00"}
