{"id":"https://openalex.org/W2161622842","doi":"https://doi.org/10.2498/cit.1000731","title":"Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations","display_name":"Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations","publication_year":2006,"publication_date":"2006-07-12","ids":{"openalex":"https://openalex.org/W2161622842","doi":"https://doi.org/10.2498/cit.1000731","mag":"2161622842"},"language":"en","primary_location":{"id":"doi:10.2498/cit.1000731","is_oa":true,"landing_page_url":"https://doi.org/10.2498/cit.1000731","pdf_url":"http://cit.fer.hr/index.php/CIT/article/download/1629/1333","source":{"id":"https://openalex.org/S98565333","display_name":"Journal of Computing and Information Technology","issn_l":"1330-1136","issn":["1330-1136","1846-3908"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310314807","host_organization_name":"Faculty of Electrical Engineering and Computing, University of Zagreb","host_organization_lineage":["https://openalex.org/P4310314807"],"host_organization_lineage_names":["Faculty of Electrical Engineering and Computing, University of Zagreb"],"type":"journal"},"license":"cc-by-nd","license_id":"https://openalex.org/licenses/cc-by-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computing and Information Technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://cit.fer.hr/index.php/CIT/article/download/1629/1333","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101674322","display_name":"Kuntal Roy","orcid":"https://orcid.org/0000-0002-1100-9073"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Kuntal Roy","raw_affiliation_strings":["Commu-nication Engineering Department of Jadavpur University","Department of Electronics and Tele-Communication Engineering, Jadavpur University, India","Department of Electronics and Tele-Communication Engineering Jadavpur University Kolkata -700 032 India"],"affiliations":[{"raw_affiliation_string":"Commu-nication Engineering Department of Jadavpur University","institution_ids":["https://openalex.org/I170979836"]},{"raw_affiliation_string":"Department of Electronics and Tele-Communication Engineering, Jadavpur University, India","institution_ids":["https://openalex.org/I170979836"]},{"raw_affiliation_string":"Department of Electronics and Tele-Communication Engineering Jadavpur University Kolkata -700 032 India","institution_ids":["https://openalex.org/I170979836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5101674322"],"corresponding_institution_ids":["https://openalex.org/I170979836"],"apc_list":{"value":450,"currency":"EUR","value_usd":485},"apc_paid":{"value":450,"currency":"EUR","value_usd":485},"fwci":0.0,"has_fulltext":true,"cited_by_count":15,"citation_normalized_percentile":{"value":0.18684453,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"15","issue":"1","first_page":"85","last_page":"85"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.9370497465133667},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.9137465357780457},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.6904056072235107},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6436312198638916},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6062787771224976},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5692496299743652},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5125024318695068},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4588083028793335},{"id":"https://openalex.org/keywords/eulers-formula","display_name":"Euler's formula","score":0.42439359426498413},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.41557803750038147},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3894383907318115},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2614419460296631},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.23277035355567932},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16631489992141724},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13674980401992798},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08653903007507324},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08178967237472534},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.07659590244293213}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9370497465133667},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9137465357780457},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.6904056072235107},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6436312198638916},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6062787771224976},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5692496299743652},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5125024318695068},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4588083028793335},{"id":"https://openalex.org/C62884695","wikidata":"https://www.wikidata.org/wiki/Q184871","display_name":"Euler's formula","level":2,"score":0.42439359426498413},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.41557803750038147},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3894383907318115},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2614419460296631},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23277035355567932},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16631489992141724},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13674980401992798},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08653903007507324},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08178967237472534},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.07659590244293213},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.2498/cit.1000731","is_oa":true,"landing_page_url":"https://doi.org/10.2498/cit.1000731","pdf_url":"http://cit.fer.hr/index.php/CIT/article/download/1629/1333","source":{"id":"https://openalex.org/S98565333","display_name":"Journal of Computing and Information Technology","issn_l":"1330-1136","issn":["1330-1136","1846-3908"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310314807","host_organization_name":"Faculty of Electrical Engineering and Computing, University of Zagreb","host_organization_lineage":["https://openalex.org/P4310314807"],"host_organization_lineage_names":["Faculty of Electrical Engineering and Computing, University of Zagreb"],"type":"journal"},"license":"cc-by-nd","license_id":"https://openalex.org/licenses/cc-by-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computing and Information Technology","raw_type":"journal-article"},{"id":"pmh:oai:hrcak.srce.hr:44640","is_oa":true,"landing_page_url":"http://hrcak.srce.hr/44640","pdf_url":null,"source":{"id":"https://openalex.org/S4306400677","display_name":"Hr\u010dak Portal of scientific journals of Croatia (University Computing Centre)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210104502","host_organization_name":"United Nations University","host_organization_lineage":["https://openalex.org/I4210104502"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Journal of computing and information technology","raw_type":"text"}],"best_oa_location":{"id":"doi:10.2498/cit.1000731","is_oa":true,"landing_page_url":"https://doi.org/10.2498/cit.1000731","pdf_url":"http://cit.fer.hr/index.php/CIT/article/download/1629/1333","source":{"id":"https://openalex.org/S98565333","display_name":"Journal of Computing and Information Technology","issn_l":"1330-1136","issn":["1330-1136","1846-3908"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310314807","host_organization_name":"Faculty of Electrical Engineering and Computing, University of Zagreb","host_organization_lineage":["https://openalex.org/P4310314807"],"host_organization_lineage_names":["Faculty of Electrical Engineering and Computing, University of Zagreb"],"type":"journal"},"license":"cc-by-nd","license_id":"https://openalex.org/licenses/cc-by-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computing and Information Technology","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2161622842.pdf","grobid_xml":"https://content.openalex.org/works/W2161622842.grobid-xml"},"referenced_works_count":5,"referenced_works":["https://openalex.org/W1519532587","https://openalex.org/W1598341975","https://openalex.org/W1987067207","https://openalex.org/W2057084070","https://openalex.org/W4212971671"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2339836056","https://openalex.org/W1811213809","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2087862887"],"abstract_inverted_index":{"The":[0,131],"paper":[1],"addresses":[2],"some":[3],"insights":[4],"into":[5],"the":[6,13,29,53,61,74,110,123,135],"Euler":[7,36,44],"path":[8,37,45],"approach":[9,38],"to":[10,71,108,133],"find":[11],"out":[12],"optimum":[14],"gate":[15,55],"ordering":[16],"of":[17,22,28,63,73,77,100,112,126,138],"CMOS":[18],"logic":[19,54],"gates.":[20],"Minimization":[21],"circuit":[23,33],"layout":[24,34,56,64],"area":[25,65],"is":[26,129,141],"one":[27],"fundamental":[30],"considerations":[31],"in":[32,46,80,144],"synthesis.":[35],"suggests":[39],"that":[40,90,122],"finding":[41],"a":[42,91],"common":[43],"both":[47],"NMOS":[48,81,113],"and":[49,82],"PMOS":[50,83,117],"network":[51,93,114,118],"minimizes":[52],"area.":[57],"In":[58],"this":[59,145],"article,":[60],"minimization":[62,72],"has":[66,86],"been":[67,87],"placed":[68],"as":[69],"equivalent":[70],"total":[75,124,136],"number":[76,99,125,137],"odd":[78,101,127],"vertices":[79,128],"networks.":[84],"It":[85],"logically":[88],"proved":[89],"MOS":[92],"will":[94],"always":[95],"have":[96],"an":[97],"even":[98],"vertices.":[102],"Moreover,":[103],"it":[104],"intuitively":[105],"explains":[106],"how":[107],"organize":[109],"sequence":[111],"when":[115],"deriving":[116],"from":[119],"it,":[120],"so":[121],"minimized.":[130],"algorithm":[132],"determine":[134],"optimized":[139],"solutions":[140],"also":[142],"presented":[143],"paper.":[146]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
