{"id":"https://openalex.org/W1970719321","doi":"https://doi.org/10.2478/s13537-011-0015-z","title":"A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure","display_name":"A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W1970719321","doi":"https://doi.org/10.2478/s13537-011-0015-z","mag":"1970719321"},"language":"en","primary_location":{"id":"doi:10.2478/s13537-011-0015-z","is_oa":true,"landing_page_url":"https://doi.org/10.2478/s13537-011-0015-z","pdf_url":"https://www.degruyter.com/document/doi/10.2478/s13537-011-0015-z/pdf","source":{"id":"https://openalex.org/S4210177004","display_name":"Open Computer Science","issn_l":"2299-1093","issn":["2299-1093"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Open Computer Science","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://www.degruyter.com/document/doi/10.2478/s13537-011-0015-z/pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009246558","display_name":"Doru Florin Chiper","orcid":"https://orcid.org/0000-0002-3322-4663"},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":true,"raw_author_name":"Doru Chiper","raw_affiliation_strings":["Department of Applied Electronics, Technical University \u201cGh. Asachi\u201d Iasi, B-dul Carol I, No.11, RO-6600, Iasi, Romania","Technical University \u201cGh. Asachi\u201d Iasi"],"affiliations":[{"raw_affiliation_string":"Department of Applied Electronics, Technical University \u201cGh. Asachi\u201d Iasi, B-dul Carol I, No.11, RO-6600, Iasi, Romania","institution_ids":["https://openalex.org/I4210108695"]},{"raw_affiliation_string":"Technical University \u201cGh. Asachi\u201d Iasi","institution_ids":["https://openalex.org/I4210108695"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5009246558"],"corresponding_institution_ids":["https://openalex.org/I4210108695"],"apc_list":{"value":1000,"currency":"EUR","value_usd":1078},"apc_paid":{"value":1000,"currency":"EUR","value_usd":1078},"fwci":0.0,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.05023621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"1","issue":"2","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11210","display_name":"Mathematical Analysis and Transform Methods","score":0.9861000180244446,"subfield":{"id":"https://openalex.org/subfields/2604","display_name":"Applied Mathematics"},"field":{"id":"https://openalex.org/fields/26","display_name":"Mathematics"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8493462204933167},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.8068838119506836},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6287095546722412},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6203916668891907},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.552388072013855},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.5460519790649414},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.5408570766448975},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5319602489471436},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5172582268714905},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4152933955192566},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.33097827434539795},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.1415623426437378},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12027797102928162},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.07099270820617676}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8493462204933167},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.8068838119506836},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6287095546722412},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6203916668891907},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.552388072013855},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.5460519790649414},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5408570766448975},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5319602489471436},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5172582268714905},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4152933955192566},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.33097827434539795},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.1415623426437378},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12027797102928162},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.07099270820617676},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.2478/s13537-011-0015-z","is_oa":true,"landing_page_url":"https://doi.org/10.2478/s13537-011-0015-z","pdf_url":"https://www.degruyter.com/document/doi/10.2478/s13537-011-0015-z/pdf","source":{"id":"https://openalex.org/S4210177004","display_name":"Open Computer Science","issn_l":"2299-1093","issn":["2299-1093"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Open Computer Science","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:7bf0c7bcd3d14192842861b74eb27399","is_oa":true,"landing_page_url":"https://doaj.org/article/7bf0c7bcd3d14192842861b74eb27399","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Open Computer Science, Vol 1, Iss 2, Pp 243-250 (2011)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.2478/s13537-011-0015-z","is_oa":true,"landing_page_url":"https://doi.org/10.2478/s13537-011-0015-z","pdf_url":"https://www.degruyter.com/document/doi/10.2478/s13537-011-0015-z/pdf","source":{"id":"https://openalex.org/S4210177004","display_name":"Open Computer Science","issn_l":"2299-1093","issn":["2299-1093"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Open Computer Science","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1970719321.pdf","grobid_xml":"https://content.openalex.org/works/W1970719321.grobid-xml"},"referenced_works_count":15,"referenced_works":["https://openalex.org/W1604949508","https://openalex.org/W1966904279","https://openalex.org/W1970975843","https://openalex.org/W2017369466","https://openalex.org/W2027735369","https://openalex.org/W2070204827","https://openalex.org/W2093708924","https://openalex.org/W2095603848","https://openalex.org/W2111513816","https://openalex.org/W2141193703","https://openalex.org/W2144640755","https://openalex.org/W2145695757","https://openalex.org/W2165634116","https://openalex.org/W2172268808","https://openalex.org/W2995746888"],"related_works":["https://openalex.org/W2165313046","https://openalex.org/W2094130026","https://openalex.org/W2022568231","https://openalex.org/W2143176207","https://openalex.org/W2038682752","https://openalex.org/W1988237207","https://openalex.org/W2127996712","https://openalex.org/W2592499194","https://openalex.org/W2142131433","https://openalex.org/W2382729611"],"abstract_inverted_index":{"Abstract":[0],"A":[1,101],"new":[2],"VLSI":[3,59,104],"algorithm":[4,44,63],"and":[5,79,123,133],"its":[6],"associated":[7],"systolic":[8,35,70],"array":[9,36,71],"architecture":[10,37,85],"for":[11,31,38,57,92,130],"a":[12,33,46,58,68,73,98],"prime":[13],"length":[14],"type":[15,39,93],"IV":[16,40,94],"discrete":[17],"cosine":[18],"transform":[19],"is":[20,55,64],"presented.":[21],"They":[22],"represent":[23],"the":[24,114],"basis":[25],"of":[26,76],"an":[27],"efficient":[28,103],"design":[29],"approach":[30],"deriving":[32],"linear":[34,69],"DCT.":[41],"The":[42,61,83],"proposed":[43,62,84],"uses":[45],"regular":[47],"computational":[48,136],"structure":[49,53],"called":[50],"pseudoband":[51],"correlation":[52,132],"that":[54,90],"appropriate":[56],"implementation.":[60],"then":[65],"mapped":[66],"onto":[67],"with":[72,89,110],"small":[74],"number":[75],"I/O":[77,81,124],"channels":[78],"low":[80],"bandwidth.":[82],"can":[86,106],"be":[87,107],"unified":[88],"obtained":[91,109,129],"DST":[95],"due":[96],"to":[97,127],"similar":[99,126],"kernel.":[100],"highly":[102],"chip":[105],"thus":[108],"good":[111],"performance":[112],"in":[113],"architectural":[115],"topology,":[116],"computing":[117],"parallelism,":[118],"processing":[119],"speed,":[120],"hardware":[121],"complexity":[122],"costs":[125],"those":[128],"circular":[131],"cyclic":[134],"convolution":[135],"structures.":[137]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}