{"id":"https://openalex.org/W2810540258","doi":"https://doi.org/10.23919/mipro.2018.8400015","title":"Timing closure of clock enable signals on a 32 nm Intel Itanium processor","display_name":"Timing closure of clock enable signals on a 32 nm Intel Itanium processor","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2810540258","doi":"https://doi.org/10.23919/mipro.2018.8400015","mag":"2810540258"},"language":"en","primary_location":{"id":"doi:10.23919/mipro.2018.8400015","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mipro.2018.8400015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 41st International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066194372","display_name":"Branimir Malnar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Branimir Malnar","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045474714","display_name":"Goran Zelic","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Goran Zelic","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5066194372"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.07840623,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"0078","last_page":"0083"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7322078943252563},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7044451236724854},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5836694836616516},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5304864048957825},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5297069549560547},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4916914105415344},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4402511715888977},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4384327232837677},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4372614026069641},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38853827118873596},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35347461700439453},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.347018301486969},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3250822424888611},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.2935090959072113},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09822037816047668}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7322078943252563},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7044451236724854},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5836694836616516},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5304864048957825},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5297069549560547},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4916914105415344},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4402511715888977},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4384327232837677},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4372614026069641},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38853827118873596},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35347461700439453},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.347018301486969},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3250822424888611},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2935090959072113},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09822037816047668},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mipro.2018.8400015","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mipro.2018.8400015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 41st International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1607075260","https://openalex.org/W2105404019","https://openalex.org/W2126475478","https://openalex.org/W2176367099","https://openalex.org/W6678717231"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2308963021","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2076992934","https://openalex.org/W4200240321","https://openalex.org/W2224788396","https://openalex.org/W2520965597","https://openalex.org/W2587665273","https://openalex.org/W2143420037"],"abstract_inverted_index":{"With":[0],"modern":[1],"high":[2,63],"speed":[3],"circuit":[4],"design":[5,40],"using":[6],"state":[7],"of":[8,18,29,34,49,58,106,114,125,174],"the":[9,52,99,107,129,155,164,168,193],"art":[10],"automated":[11,123],"place":[12],"and":[13,66,109,158,176,190,192],"route":[14],"(APR)":[15],"flows,":[16],"synthesis":[17,76],"clock":[19,115],"enable":[20],"(CE)":[21],"signals":[22,85],"is":[23,44,91,148],"becoming":[24],"increasingly":[25],"difficult":[26,78],"in":[27,37,41,128,163],"terms":[28],"timing":[30,80,134,146],"closure.":[31],"The":[32,88],"size":[33],"APR":[35,72,130],"blocks":[36,73],"digital":[38],"physical":[39,156],"microprocessor":[42],"projects":[43],"expanding":[45],"with":[46,62,159,171],"every":[47],"generation":[48],"microprocessors":[50],"as":[51,79],"implementation":[53],"tools":[54],"become":[55],"more":[56,177],"capable":[57],"handling":[59],"large":[60],"designs":[61],"quality":[64],"results":[65],"fast":[67],"turnaround":[68],"times.":[69],"However,":[70],"larger":[71,104],"make":[74],"CE":[75,96,126,169],"progressively":[77],"closure":[81,135],"complexity":[82],"on":[83,136,183],"these":[84],"increases":[86],"dramatically.":[87],"main":[89],"problem":[90,170],"due":[92],"to":[93,101,110,132,167],"a":[94,102,111,137],"single":[95],"register":[97],"driving":[98],"signal":[100],"relatively":[103],"area":[105],"design,":[108],"greater":[112],"number":[113],"gating":[116],"cells.":[117],"In":[118],"this":[119],"paper,":[120],"we":[121],"present":[122],"duplication":[124],"logic":[127],"flow":[131],"achieve":[133],"32":[138],"nm":[139],"Intel":[140],"Itanium":[141],"project.":[142],"We":[143],"show":[144],"how":[145],"convergence":[147],"achieved":[149],"without":[150],"any":[151],"additional":[152],"effort":[153],"from":[154],"designers,":[157],"no":[160],"changes":[161],"required":[162],"RTL.":[165],"Solutions":[166],"smaller":[172],"degree":[173],"automation":[175],"manual":[178],"effort,":[179],"which":[180],"were":[181],"used":[182],"our":[184],"previous":[185],"projects,":[186],"are":[187,196,199],"also":[188],"discussed":[189],"compared,":[191],"reasons":[194],"they":[195],"deemed":[197],"inadequate":[198],"explained.":[200]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
