{"id":"https://openalex.org/W4385209678","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185432","title":"A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing","display_name":"A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing","publication_year":2023,"publication_date":"2023-06-11","ids":{"openalex":"https://openalex.org/W4385209678","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185432"},"language":"en","primary_location":{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185432","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185432","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101434890","display_name":"Kenta Suzuki","orcid":"https://orcid.org/0000-0001-6525-4704"},"institutions":[{"id":"https://openalex.org/I1304132090","display_name":"Sony (Taiwan)","ror":"https://ror.org/0214y7014","country_code":"TW","type":"company","lineage":["https://openalex.org/I1304132090","https://openalex.org/I4210143797"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kenta Suzuki","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation","institution_ids":["https://openalex.org/I1304132090"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041270546","display_name":"Keizo Hiraga","orcid":null},"institutions":[{"id":"https://openalex.org/I1304132090","display_name":"Sony (Taiwan)","ror":"https://ror.org/0214y7014","country_code":"TW","type":"company","lineage":["https://openalex.org/I1304132090","https://openalex.org/I4210143797"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Keizo Hiraga","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation","institution_ids":["https://openalex.org/I1304132090"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109677544","display_name":"Kazuhiro Bessho","orcid":null},"institutions":[{"id":"https://openalex.org/I1304132090","display_name":"Sony (Taiwan)","ror":"https://ror.org/0214y7014","country_code":"TW","type":"company","lineage":["https://openalex.org/I1304132090","https://openalex.org/I4210143797"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kazuhiro Bessho","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation","institution_ids":["https://openalex.org/I1304132090"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030692253","display_name":"Kimiyoshi Usami","orcid":"https://orcid.org/0000-0002-8911-3313"},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kimiyoshi Usami","raw_affiliation_strings":["Shibaura Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shibaura Institute of Technology","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040968347","display_name":"Taku Umebayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I1304132090","display_name":"Sony (Taiwan)","ror":"https://ror.org/0214y7014","country_code":"TW","type":"company","lineage":["https://openalex.org/I1304132090","https://openalex.org/I4210143797"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Taku Umebayashi","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation","institution_ids":["https://openalex.org/I1304132090"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9298242926597595},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.6329740881919861},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6156842112541199},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5202768445014954},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5148109793663025},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4940107464790344},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.47513487935066223},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47048309445381165},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45204147696495056},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4324219226837158},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07608678936958313}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9298242926597595},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.6329740881919861},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6156842112541199},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5202768445014954},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5148109793663025},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4940107464790344},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.47513487935066223},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47048309445381165},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45204147696495056},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4324219226837158},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07608678936958313},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185432","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185432","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2119312496","https://openalex.org/W2110321764","https://openalex.org/W4247460323","https://openalex.org/W2783549708","https://openalex.org/W2537086382","https://openalex.org/W2107909712","https://openalex.org/W2036350002","https://openalex.org/W2153162275","https://openalex.org/W2079259690","https://openalex.org/W2023834321"],"abstract_inverted_index":{"We":[0,61],"propose":[1],"a":[2,53,63,69,91],"magnetic":[3],"tunnel":[4],"junction":[5],"(MTJ)-based":[6],"nonvolatile":[7],"SRAM":[8,21],"(NVSRAM)":[9],"to":[10,77],"obtain":[11],"normally":[12],"off":[13],"computing.":[14],"The":[15,87],"proposed":[16],"NVSRAM":[17],"not":[18],"only":[19],"combines":[20],"performance":[22],"and":[23,52,94],"non-volatility":[24],"but":[25],"also":[26],"shows":[27],"improved":[28],"area":[29],"efficiency":[30],"by":[31,48,67,99],"sharing":[32],"the":[33,39,79,100],"driver":[34],"with":[35,73],"peripheral":[36],"circuits.":[37],"Moreover,":[38],"data-aware":[40],"store":[41,46,96,101],"scheme":[42],"enables":[43],"reduction":[44,98],"in":[45],"energy":[47,97],"data":[49],"comparison":[50],"control":[51,102],"verify":[54],"operation":[55],"that":[56],"mitigates":[57],"MTJ":[58],"process":[59,72],"variation.":[60],"fabricated":[62],"2":[64],"kb":[65],"macro":[66],"using":[68],"40":[70],"nm":[71],"optimized":[74],"memory":[75],"cells":[76],"overcome":[78],"risk":[80],"of":[81,84],"latch":[82],"destruction":[83],"conventional":[85],"cells.":[86],"measurement":[88],"results":[89],"demonstrated":[90],"non-volatile":[92],"function":[93],"3.5x":[95],"optimization.":[103]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}