{"id":"https://openalex.org/W4385192476","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185311","title":"A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality","display_name":"A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality","publication_year":2023,"publication_date":"2023-06-11","ids":{"openalex":"https://openalex.org/W4385192476","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185311"},"language":"en","primary_location":{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185311","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041367243","display_name":"Yuhao Ju","orcid":"https://orcid.org/0000-0003-2509-400X"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuhao Ju","raw_affiliation_strings":["Northwestern University,Evanston,IL,USA","Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northwestern University,Evanston,IL,USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023535233","display_name":"Yijie Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yijie Wei","raw_affiliation_strings":["Northwestern University,Evanston,IL,USA","Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northwestern University,Evanston,IL,USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100330050","display_name":"Xi Chen","orcid":"https://orcid.org/0000-0003-4221-4288"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xi Chen","raw_affiliation_strings":["Northwestern University,Evanston,IL,USA","Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northwestern University,Evanston,IL,USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005991726","display_name":"Jie Gu","orcid":"https://orcid.org/0000-0003-2912-7294"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jie Gu","raw_affiliation_strings":["Northwestern University,Evanston,IL,USA","Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northwestern University,Evanston,IL,USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I111979921"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8290351629257202},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8212690353393555},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.7667882442474365},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6502508521080017},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.5127502679824829},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.48771747946739197},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.46550944447517395},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.43878284096717834},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43616583943367004},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.4222947657108307},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.4148736298084259},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3755452036857605},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.301102876663208},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21908286213874817}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8290351629257202},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8212690353393555},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.7667882442474365},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6502508521080017},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.5127502679824829},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.48771747946739197},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.46550944447517395},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.43878284096717834},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43616583943367004},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.4222947657108307},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.4148736298084259},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3755452036857605},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.301102876663208},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21908286213874817},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185311","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7200000286102295,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2355267286","https://openalex.org/W4377693460","https://openalex.org/W4320067870","https://openalex.org/W2670084885","https://openalex.org/W2040778456","https://openalex.org/W3089727897","https://openalex.org/W4229759254","https://openalex.org/W2905159200","https://openalex.org/W2151773378","https://openalex.org/W2403596187"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,26,33,42],"general-purpose":[4],"compute-in-memory":[5],"(GPCIM)":[6],"processor":[7],"combining":[8],"DNN":[9,29],"operations":[10],"and":[11,18,32],"vector":[12],"CPU.":[13],"Utilizing":[14],"special":[15],"reconfigurability,":[16],"dataflow,":[17],"instruction":[19],"set,":[20],"the":[21],"65nm":[22],"test":[23],"chip":[24],"demonstrates":[25],"28.5":[27],"TOPS/W":[28],"macro":[30],"efficiency":[31,37],"best-in-class":[34],"peak":[35],"CPU":[36],"of":[38],"802GOPS/W.":[39],"Due":[40],"to":[41,47],"data":[43,60],"locality":[44],"flow,":[45],"37%":[46],"55%":[48],"end-to-end":[49],"latency":[50],"improvement":[51],"on":[52],"AI-related":[53],"applications":[54],"is":[55],"achieved":[56],"by":[57],"eliminating":[58],"inter-core":[59],"transfer.":[61]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}