{"id":"https://openalex.org/W4385196313","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185227","title":"Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN)","display_name":"Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN)","publication_year":2023,"publication_date":"2023-06-11","ids":{"openalex":"https://openalex.org/W4385196313","doi":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185227"},"language":"en","primary_location":{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185227","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051712390","display_name":"Eric Beyne","orcid":"https://orcid.org/0000-0002-3096-050X"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Eric Beyne","raw_affiliation_strings":["Geert van der Plas imec,Leuven,Belgium","Geert van der Plas imec, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Geert van der Plas imec,Leuven,Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"Geert van der Plas imec, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061504157","display_name":"Anne Jourdain","orcid":"https://orcid.org/0000-0002-5741-3020"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Anne Jourdain","raw_affiliation_strings":["Geert van der Plas imec,Leuven,Belgium","Geert van der Plas imec, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Geert van der Plas imec,Leuven,Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"Geert van der Plas imec, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112402799","display_name":"Gerald Beyer","orcid":"https://orcid.org/0009-0009-6367-3046"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Gerald Beyer","raw_affiliation_strings":["Geert van der Plas imec,Leuven,Belgium","Geert van der Plas imec, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Geert van der Plas imec,Leuven,Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"Geert van der Plas imec, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210114974"],"apc_list":null,"apc_paid":null,"fwci":2.1825,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.87893856,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.8438653349876404},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6730078458786011},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.6120932102203369},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6046125888824463},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.5990980863571167},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.5357562303543091},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.49481385946273804},{"id":"https://openalex.org/keywords/wafer-bonding","display_name":"Wafer bonding","score":0.4880336821079254},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42770785093307495},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42736637592315674},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42660945653915405},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.42283836007118225},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4073716104030609},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37469127774238586},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.34678518772125244},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22274821996688843},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10030126571655273},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07220911979675293}],"concepts":[{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.8438653349876404},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6730078458786011},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.6120932102203369},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6046125888824463},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.5990980863571167},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.5357562303543091},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.49481385946273804},{"id":"https://openalex.org/C2779133538","wikidata":"https://www.wikidata.org/wiki/Q677010","display_name":"Wafer bonding","level":3,"score":0.4880336821079254},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42770785093307495},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42736637592315674},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42660945653915405},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.42283836007118225},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4073716104030609},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37469127774238586},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.34678518772125244},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22274821996688843},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10030126571655273},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07220911979675293},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/vlsitechnologyandcir57934.2023.10185227","is_oa":false,"landing_page_url":"https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W3102668149","https://openalex.org/W3198195914","https://openalex.org/W4312051170"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4249035840","https://openalex.org/W2766970861","https://openalex.org/W3125341812","https://openalex.org/W1668171714","https://openalex.org/W1983191281","https://openalex.org/W2018670357","https://openalex.org/W2033407695","https://openalex.org/W2011967496"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"discuss":[4],"the":[5,31,34,49,54,64,81],"driving":[6],"forces":[7],"for":[8,22,92],"moving":[9],"to":[10,90],"chip":[11,32],"backside":[12,60],"power":[13,40],"delivery.":[14],"Possible":[15],"integration":[16,42,72],"flows":[17,73],"and":[18,51,70,86,99],"challenges":[19,79],"are":[20,80],"discussed":[21],"integrating":[23],"through-silicon":[24],"via":[25],"(TSV)":[26],"connections":[27],"that":[28,44],"directly":[29,57],"interconnect":[30],"at":[33],"standard-cell":[35],"level.":[36],"These":[37],"approaches":[38],"use":[39],"rail":[41],"schemes":[43],"can":[45],"be":[46],"\u201cburied\u201d":[47],"in":[48],"STI":[50],"Si":[52],"below":[53],"devices":[55],"or":[56],"integrated":[58],"as":[59],"metallization":[61],"scheme":[62],"on":[63],"wafer":[65,83,93,97],"backside.":[66],"Both":[67],"nTSV":[68],"\u201clast\u201d":[69],"\u201cfirst\u201d":[71],"have":[74],"been":[75],"demonstrated.":[76],"Key":[77],"technology":[78],"extreme":[82],"thinning":[84],"required":[85],"back-side":[87],"lithography":[88],"correction":[89],"correct":[91],"distortions":[94],"caused":[95],"by":[96],"processing":[98],"W2W":[100],"bonding.":[101]},"counts_by_year":[{"year":2026,"cited_by_count":5},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}