{"id":"https://openalex.org/W2903021638","doi":"https://doi.org/10.23919/seeda-cecnsm.2018.8544930","title":"Operation Dependencies in Loop Pipelining for High-Level Synthesis","display_name":"Operation Dependencies in Loop Pipelining for High-Level Synthesis","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2903021638","doi":"https://doi.org/10.23919/seeda-cecnsm.2018.8544930","mag":"2903021638"},"language":"en","primary_location":{"id":"doi:10.23919/seeda-cecnsm.2018.8544930","is_oa":false,"landing_page_url":"https://doi.org/10.23919/seeda-cecnsm.2018.8544930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 South-Eastern European Design Automation, Computer Engineering, Computer Networks and Society Media Conference (SEEDA_CECNSM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075745979","display_name":"Georgios Dimitriou","orcid":"https://orcid.org/0000-0002-1726-9044"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Georgios Dimitriou","raw_affiliation_strings":["Dept. of Computer Science, University of Thessaly, Lamia, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science, University of Thessaly, Lamia, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103219021","display_name":"Michael Dossis","orcid":"https://orcid.org/0000-0002-0178-2054"},"institutions":[{"id":"https://openalex.org/I149588736","display_name":"Technological Educational Institute of Central Macedonia","ror":"https://ror.org/01mw24p94","country_code":"GR","type":"education","lineage":["https://openalex.org/I149588736"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Michael Dossis","raw_affiliation_strings":["Dept. of Inf. Engineering, TEI of W. Macedonia, Kastoria, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Inf. Engineering, TEI of W. Macedonia, Kastoria, Greece","institution_ids":["https://openalex.org/I149588736"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065041833","display_name":"Georgios Stamoulis","orcid":"https://orcid.org/0000-0001-7248-8197"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Stamoulis","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5075745979"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.5263,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65206275,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8349356651306152},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8113597631454468},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.6755033731460571},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.6313292980194092},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.5689285397529602},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5343540906906128},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5187673568725586},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4753936529159546},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.46090683341026306},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4378885328769684},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4262273907661438},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4229414463043213},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3315408527851105},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2941023111343384},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2782573699951172},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.12277892231941223}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8349356651306152},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8113597631454468},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.6755033731460571},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.6313292980194092},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.5689285397529602},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5343540906906128},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5187673568725586},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4753936529159546},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.46090683341026306},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4378885328769684},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4262273907661438},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4229414463043213},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3315408527851105},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2941023111343384},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2782573699951172},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.12277892231941223},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.23919/seeda-cecnsm.2018.8544930","is_oa":false,"landing_page_url":"https://doi.org/10.23919/seeda-cecnsm.2018.8544930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 South-Eastern European Design Automation, Computer Engineering, Computer Networks and Society Media Conference (SEEDA_CECNSM)","raw_type":"proceedings-article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/73335","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/73335","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference, SEEDA_CECNSM 2018","raw_type":"conferenceItem"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W42313609","https://openalex.org/W1977813547","https://openalex.org/W1996464317","https://openalex.org/W2071189607","https://openalex.org/W2082085231","https://openalex.org/W2091452063","https://openalex.org/W2098515772","https://openalex.org/W2115572397","https://openalex.org/W2138092512","https://openalex.org/W2165187428","https://openalex.org/W2507391457","https://openalex.org/W2620932626","https://openalex.org/W2765564141","https://openalex.org/W4239489018","https://openalex.org/W6674431967"],"related_works":["https://openalex.org/W1519734376","https://openalex.org/W2066067904","https://openalex.org/W2921149022","https://openalex.org/W4253352037","https://openalex.org/W4238125332","https://openalex.org/W4299303078","https://openalex.org/W2063951580","https://openalex.org/W2002505081","https://openalex.org/W2083681681","https://openalex.org/W2951816406"],"abstract_inverted_index":{"Research":[0],"and":[1,64,115,120,166,183],"industry":[2],"interest":[3],"in":[4,10,37,43,68,73,139,195],"high-level":[5,79,170],"synthesis":[6,80],"has":[7],"been":[8],"renewed":[9],"the":[11,17,74,107,146,154,181,196],"last":[12],"few":[13],"years,":[14],"proven":[15],"by":[16],"introduction":[18],"of":[19,25,99,156,198],"new":[20,38],"tools":[21,29,53,81],"or":[22,32],"improved":[23],"versions":[24,39],"existing":[26],"tools.":[27],"Academic":[28],"like":[30,54],"Gaut":[31],"CCC":[33,182,188],"have":[34,62,82],"recently":[35],"appeared":[36,63],"with":[40,124,177],"expanded":[41],"functionality":[42],"order":[44],"to":[45,71,84,96],"cover":[46],"increased":[47],"hardware":[48,116],"design":[49],"requirements.":[50],"Likewise,":[51],"industrial":[52],"Xilinx":[55],"VivadoHLS":[56,184,194],"or,":[57],"more":[58],"recently,":[59],"Cadence":[60],"Stratus":[61],"are":[65,92,105],"continuously":[66],"evolving":[67],"their":[69,167],"effort":[70],"succeed":[72],"market.":[75],"One":[76],"technology":[77],"that":[78,187],"chosen":[83],"invest":[85],"on":[86,169,180],"is":[87],"compiler-driven":[88],"code":[89],"optimizations,":[90,111,141],"which":[91],"a":[93,136],"promising":[94],"means":[95],"improve":[97],"efficiency":[98],"automatically":[100],"generated":[101],"hardware.":[102],"Loop":[103,118],"transformations":[104],"among":[106,158],"most":[108],"popular":[109],"compiler":[110],"for":[112,145],"both":[113],"software":[114],"targets.":[117],"unrolling":[119],"loop":[121,159],"pipelining,":[122],"coupled":[123],"careful":[125],"instruction":[126],"reordering,":[127],"can":[128,189],"deliver":[129,190],"highly":[130],"optimized":[131],"output.":[132],"Instruction":[133],"dependencies":[134,157],"play":[135],"significant":[137],"role":[138],"such":[140],"limiting":[142],"performance":[143],"improvement":[144],"final":[147],"code.":[148],"In":[149],"this":[150],"paper,":[151],"we":[152],"discuss":[153],"issue":[155],"body":[160],"operations,":[161],"especially":[162],"those":[163],"forming":[164],"cycles,":[165],"impact":[168],"synthesis.":[171],"We":[172],"present":[173],"results":[174],"from":[175],"experiments":[176],"several":[178],"benchmarks":[179],"tools,":[185],"showing":[186],"better":[191],"output":[192],"than":[193],"presence":[197],"complex":[199],"operation":[200],"dependence":[201],"cycles.":[202]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2018-12-11T00:00:00"}
