{"id":"https://openalex.org/W4401247432","doi":"https://doi.org/10.23919/mixdes62605.2024.10614028","title":"Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology","display_name":"Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology","publication_year":2024,"publication_date":"2024-06-27","ids":{"openalex":"https://openalex.org/W4401247432","doi":"https://doi.org/10.23919/mixdes62605.2024.10614028"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes62605.2024.10614028","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/mixdes62605.2024.10614028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052653425","display_name":"Bartosz Dec","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Bartosz Dec","raw_affiliation_strings":["Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109012607","display_name":"Andrzej Pfitzner","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Andrzej Pfitzner","raw_affiliation_strings":["Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I108403487"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"193","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9840999841690063,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9735000133514404,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/trap","display_name":"Trap (plumbing)","score":0.8033084869384766},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6165956854820251},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5585148930549622},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4369537830352783},{"id":"https://openalex.org/keywords/charge","display_name":"Charge (physics)","score":0.4249672591686249},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3587932884693146},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3228580355644226},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3175848126411438},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2929539084434509},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.26258766651153564},{"id":"https://openalex.org/keywords/environmental-science","display_name":"Environmental science","score":0.1801546812057495},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11995863914489746},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.054248154163360596}],"concepts":[{"id":"https://openalex.org/C121099081","wikidata":"https://www.wikidata.org/wiki/Q665580","display_name":"Trap (plumbing)","level":2,"score":0.8033084869384766},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6165956854820251},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5585148930549622},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4369537830352783},{"id":"https://openalex.org/C188082385","wikidata":"https://www.wikidata.org/wiki/Q73792","display_name":"Charge (physics)","level":2,"score":0.4249672591686249},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3587932884693146},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3228580355644226},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3175848126411438},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2929539084434509},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.26258766651153564},{"id":"https://openalex.org/C39432304","wikidata":"https://www.wikidata.org/wiki/Q188847","display_name":"Environmental science","level":0,"score":0.1801546812057495},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11995863914489746},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.054248154163360596},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes62605.2024.10614028","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/mixdes62605.2024.10614028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2013303465","https://openalex.org/W2015244625","https://openalex.org/W2111865441","https://openalex.org/W2168060209","https://openalex.org/W2735678755","https://openalex.org/W2886117952","https://openalex.org/W2887540264","https://openalex.org/W4214479146","https://openalex.org/W4365799988","https://openalex.org/W6638836966","https://openalex.org/W6676777394","https://openalex.org/W6682504405","https://openalex.org/W6683820115"],"related_works":["https://openalex.org/W3165307257","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W4226211266","https://openalex.org/W2991151827","https://openalex.org/W2130440338","https://openalex.org/W1574518580","https://openalex.org/W2791832526","https://openalex.org/W2161229876","https://openalex.org/W4361799621"],"abstract_inverted_index":{"This":[0,41,75],"paper":[1],"presents":[2],"a":[3,91],"study":[4],"of":[5,10,14,56,72,82],"increased":[6],"information":[7,73],"storage":[8],"capabilities":[9],"single":[11,92],"memory":[12,42,57,89],"cell":[13,58],"new":[15,78],"3D":[16],"design.":[17],"Memory":[18],"was":[19],"designed":[20],"for":[21,80],"integration":[22,81],"with":[23,47,86,94],"VeSTIC":[24],"(Vertical":[25],"Slit":[26],"Transistor-based":[27],"Integrated":[28],"Circuits)":[29],"technology,":[30],"to":[31,36,65],"increase":[32],"the":[33,63],"circuit":[34],"density":[35],"effectively":[37],"use":[38],"available":[39],"space.":[40],"operates":[43],"in":[44,90],"relative":[45],"environment,":[46],"control":[48],"voltage":[49],"not":[50],"exceeding":[51],"9":[52],"V.":[53],"Test":[54],"simulations":[55],"indicate,":[59],"that":[60],"it":[61],"has":[62],"capability":[64],"hold":[66],"even":[67],"more":[68],"than":[69],"2":[70],"bits":[71],"data.":[74],"design":[76],"opens":[77],"possibilities":[79],"advanced":[83],"integrated":[84],"circuits":[85],"dedicated":[87],"non-volatile":[88],"chip":[93],"maximum":[95],"device":[96],"density.":[97]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}