{"id":"https://openalex.org/W4401248505","doi":"https://doi.org/10.23919/mixdes62605.2024.10614026","title":"Hardware Acceleration Method Using RISC-V Core with No ISA Extensions","display_name":"Hardware Acceleration Method Using RISC-V Core with No ISA Extensions","publication_year":2024,"publication_date":"2024-06-27","ids":{"openalex":"https://openalex.org/W4401248505","doi":"https://doi.org/10.23919/mixdes62605.2024.10614026"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes62605.2024.10614026","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes62605.2024.10614026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5106251802","display_name":"Mateusz Wygrzvwalski","orcid":null},"institutions":[{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Mateusz Wygrzvwalski","raw_affiliation_strings":["AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland"],"affiliations":[{"raw_affiliation_string":"AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland","institution_ids":["https://openalex.org/I686019"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033114078","display_name":"Pawe\u0142 Skrzypiec","orcid":"https://orcid.org/0000-0003-2818-0210"},"institutions":[{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Pawel Skrzypiec","raw_affiliation_strings":["AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland"],"affiliations":[{"raw_affiliation_string":"AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland","institution_ids":["https://openalex.org/I686019"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042247728","display_name":"R. Szczygie\u0142","orcid":"https://orcid.org/0000-0001-6342-0107"},"institutions":[{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Robert Szczygiel","raw_affiliation_strings":["AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland"],"affiliations":[{"raw_affiliation_string":"AGH University of Krakow,Department of Measurement and Electronics,Krakow,Poland","institution_ids":["https://openalex.org/I686019"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5106251802"],"corresponding_institution_ids":["https://openalex.org/I686019"],"apc_list":null,"apc_paid":null,"fwci":1.5594,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.83224818,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"269"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9717000126838684,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.964900016784668,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7447935938835144},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.5573851466178894},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5411298871040344},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5099142789840698},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4498511850833893},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44885891675949097},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.33049294352531433},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09724771976470947},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08188372850418091}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7447935938835144},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.5573851466178894},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5411298871040344},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5099142789840698},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4498511850833893},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44885891675949097},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.33049294352531433},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09724771976470947},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08188372850418091},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes62605.2024.10614026","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes62605.2024.10614026","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2953568773","https://openalex.org/W3016085798","https://openalex.org/W3021991761","https://openalex.org/W3135053459","https://openalex.org/W3187954618","https://openalex.org/W3191906639","https://openalex.org/W3198652786","https://openalex.org/W3217272717","https://openalex.org/W4210722209","https://openalex.org/W4384947555"],"related_works":["https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W4310584696","https://openalex.org/W4385730960","https://openalex.org/W4237840813","https://openalex.org/W4364295250","https://openalex.org/W2128502296","https://openalex.org/W2993622674","https://openalex.org/W1833044483","https://openalex.org/W4382053335"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,11,58],"method":[3],"for":[4],"hardware":[5],"acceleration":[6],"of":[7,89,107,109],"different":[8],"algorithms":[9],"using":[10],"specially":[12],"designed":[13],"RISC-V":[14],"core.":[15],"Acceleration":[16],"is":[17,57],"handled":[18],"by":[19,114],"only":[20],"CSR":[21],"registers":[22],"without":[23],"adding":[24],"any":[25],"new":[26],"instruction":[27],"to":[28,47,65,71,96,103,117],"the":[29,50,73,77,87,91,105,110,118],"Instruction":[30],"Set":[31],"Architecture":[32],"(ISA).":[33],"The":[34,54],"core":[35,55],"microarchitecture":[36],"was":[37],"extended":[38],"and":[39,61],"it":[40],"operates":[41],"in":[42,86],"several":[43],"modes,":[44,76],"which":[45],"allow":[46],"speed":[48],"up":[49],"code":[51,79],"being":[52],"executed.":[53],"modification":[56],"general":[59],"purpose":[60],"can":[62],"be":[63,69,81],"applied":[64],"other":[66],"cores.":[67],"To":[68],"able":[70,102],"use":[72],"processor":[74],"operating":[75],"assembly":[78,120],"must":[80],"appropriately":[82],"modified,":[83],"as":[84],"shown":[85],"example":[88],"calculating":[90],"Number":[92],"Theoretic-Transform":[93],"(NTT).":[94],"Thanks":[95],"such":[97],"hardware/software":[98],"approach":[99],"we":[100],"were":[101],"reduce":[104],"number":[106],"cycles":[108],"Kyber":[111],"NTT":[112],"algorithm":[113],"30%":[115],"compared":[116],"optimized":[119],"program.":[121]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-02-25T08:12:03.925757","created_date":"2025-10-10T00:00:00"}
