{"id":"https://openalex.org/W4385694722","doi":"https://doi.org/10.23919/mixdes58562.2023.10203264","title":"A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems","display_name":"A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems","publication_year":2023,"publication_date":"2023-06-29","ids":{"openalex":"https://openalex.org/W4385694722","doi":"https://doi.org/10.23919/mixdes58562.2023.10203264"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes58562.2023.10203264","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/mixdes58562.2023.10203264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006313189","display_name":"Guido Di Patrizio Stanchieri","orcid":"https://orcid.org/0000-0001-5279-6627"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Guido Di Patrizio Stanchieri","raw_affiliation_strings":["Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071885582","display_name":"Andrea De Marcellis","orcid":"https://orcid.org/0000-0003-2490-7486"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea De Marcellis","raw_affiliation_strings":["Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008675649","display_name":"Marco Faccio","orcid":"https://orcid.org/0000-0002-2856-7733"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Faccio","raw_affiliation_strings":["Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026408860","display_name":"E. Palange","orcid":"https://orcid.org/0000-0002-2173-9985"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Elia Palange","raw_affiliation_strings":["Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068038161","display_name":"Orazio Aiello","orcid":"https://orcid.org/0000-0002-6938-9806"},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Orazio Aiello","raw_affiliation_strings":["Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa,Dept. of Electrical,Genoa,Italy","Dept. of Electrical, Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa, Genoa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa,Dept. of Electrical,Genoa,Italy","institution_ids":["https://openalex.org/I83816512"]},{"raw_affiliation_string":"Dept. of Electrical, Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6158,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.89543773,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.8640118837356567},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6273922324180603},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5856203436851501},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5286510586738586},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4924691617488861},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4924374520778656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4699654281139374},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.4384618401527405},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4362945854663849},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4362805187702179},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4320390522480011},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4252014756202698},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3820527493953705},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2915147542953491}],"concepts":[{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.8640118837356567},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6273922324180603},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5856203436851501},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5286510586738586},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4924691617488861},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4924374520778656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4699654281139374},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.4384618401527405},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4362945854663849},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4362805187702179},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4320390522480011},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4252014756202698},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3820527493953705},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2915147542953491},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes58562.2023.10203264","is_oa":false,"landing_page_url":"http://dx.doi.org/10.23919/mixdes58562.2023.10203264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8600000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1999245428","https://openalex.org/W2003275364","https://openalex.org/W2006630962","https://openalex.org/W2126227985","https://openalex.org/W2160173333","https://openalex.org/W2163095973","https://openalex.org/W2277822878","https://openalex.org/W2340566934","https://openalex.org/W2545422235","https://openalex.org/W2559322713","https://openalex.org/W2568685774","https://openalex.org/W2624563526","https://openalex.org/W2803950919","https://openalex.org/W2906248357","https://openalex.org/W3091142092","https://openalex.org/W3118227685","https://openalex.org/W3128536225","https://openalex.org/W3158167365","https://openalex.org/W3177178868","https://openalex.org/W3211324026","https://openalex.org/W4200197932","https://openalex.org/W4223966376","https://openalex.org/W4285259100"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2169622190","https://openalex.org/W2224788396","https://openalex.org/W3013924136","https://openalex.org/W2143420037","https://openalex.org/W2615366277","https://openalex.org/W2151256709","https://openalex.org/W4238381000","https://openalex.org/W2139338465","https://openalex.org/W2119143324"],"abstract_inverted_index":{"This":[0,53,178],"paper":[1],"reports":[2],"on":[3],"a":[4,11,18,35,70,92,100,108,142,185],"Duty-Cycle":[5],"Corrector":[6],"(DCC)":[7],"circuit":[8,37,81,121,163,182],"that":[9,64],"employs":[10],"closed-loop":[12],"scheme":[13],"paradigm":[14],"capable":[15],"to":[16,39,72,123,137,175],"provide":[17],"real":[19],"time":[20],"50%":[21],"duty-cycle":[22,130,145],"control":[23,31,54],"of":[24,43,46,61,104,111,146,187],"the":[25,41,44,47,59,74,119,126,147,159,180],"generated":[26,33],"output":[27,50,75,148],"clock":[28,51,76,128,149,166,191],"signal.":[29],"A":[30],"voltage":[32,55,97],"by":[34],"feedback":[36],"allows":[38],"estimate":[40],"values":[42,60,132],"duty-cycles":[45],"input":[48,127,165],"and":[49,57,66,98,202],"signals.":[52],"provides":[56],"regulates":[58],"two":[62],"currents":[63],"charge":[65],"discharge,":[67],"even":[68],"asymmetrically,":[69],"load":[71],"adjust":[73],"signal":[77,129,150],"duty-cycle.":[78],"The":[79,114],"DCC":[80,120,162],"has":[82],"been":[83],"designed":[84],"in":[85],"TSMC":[86],"180":[87],"nm":[88],"CMOS":[89],"technology":[90],"with":[91,151,168],"1.8":[93],"V":[94],"single":[95],"supply":[96],"requires":[99],"total":[101],"Si":[102],"area":[103],"about":[105],"0.017":[106],"mm2with":[107],"power":[109],"consumption":[110],"0.46":[112],"mW/GHz.":[113],"reported":[115],"post-layout":[116],"simulations":[117],"validated":[118],"performances":[122],"suitable":[124,183],"correct":[125],"for":[131,184],"ranging":[133,170],"from":[134,171],"30":[135,176],"%":[136,139,144],"70":[138],"so":[140],"providing":[141],"50":[143],"an":[152],"error":[153],"smaller":[154],"than":[155],"\u00b11":[156],"%.":[157],"Furthermore,":[158],"proposed":[160],"simple":[161],"handles":[164],"waveforms":[167],"frequencies":[169],"3":[172],"GHz":[173],"down":[174],"kHz.":[177],"makes":[179],"DDC":[181],"variety":[186],"applications":[188],"such":[189],"as":[190],"generators,":[192],"transceivers,":[193],"serial":[194],"interfaces,":[195],"Phase-Locked":[196],"Loop,":[197,199],"Delay-Locked":[198],"RAM":[200],"memories,":[201],"data":[203],"links.":[204]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}