{"id":"https://openalex.org/W2888450017","doi":"https://doi.org/10.23919/mixdes.2018.8443590","title":"A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18\u03bcm Technology","display_name":"A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18\u03bcm Technology","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2888450017","doi":"https://doi.org/10.23919/mixdes.2018.8443590","mag":"2888450017"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes.2018.8443590","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8443590","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048269716","display_name":"Faeze Noruzpur","orcid":null},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Faeze Noruzpur","raw_affiliation_strings":["Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025975068","display_name":"Sina Mahdavi","orcid":null},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Sina Mahdavi","raw_affiliation_strings":["Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069907496","display_name":"Maryam Poreh","orcid":null},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Maryam Poreh","raw_affiliation_strings":["Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073105442","display_name":"Shima Tayyeb Ghasemi","orcid":null},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Shima Tayyeb Ghasemi","raw_affiliation_strings":["Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048269716"],"corresponding_institution_ids":["https://openalex.org/I38476204"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.47935087,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"109","last_page":"115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9466732740402222},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9113849401473999},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5424355864524841},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5147750377655029},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4827291667461395},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.47875016927719116},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36707353591918945},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2727901041507721},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20333555340766907},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13900279998779297}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9466732740402222},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9113849401473999},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5424355864524841},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5147750377655029},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4827291667461395},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.47875016927719116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36707353591918945},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2727901041507721},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20333555340766907},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13900279998779297},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes.2018.8443590","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8443590","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W103546617","https://openalex.org/W104058094","https://openalex.org/W1890716699","https://openalex.org/W1965272013","https://openalex.org/W2022851692","https://openalex.org/W2025440251","https://openalex.org/W2034597864","https://openalex.org/W2038555165","https://openalex.org/W2058945477","https://openalex.org/W2104147443","https://openalex.org/W2118186585","https://openalex.org/W2153267648","https://openalex.org/W2154331325","https://openalex.org/W2170216809","https://openalex.org/W2283488694","https://openalex.org/W2307766266","https://openalex.org/W2406676249","https://openalex.org/W2734842153","https://openalex.org/W2786692488","https://openalex.org/W2786841920","https://openalex.org/W3098158272","https://openalex.org/W4242378741","https://openalex.org/W6604312196","https://openalex.org/W6677227518","https://openalex.org/W6741415766"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W2058044441","https://openalex.org/W3117675750","https://openalex.org/W2139484866","https://openalex.org/W4225994594","https://openalex.org/W2109445684"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,127],"new":[4],"semi-digital":[5],"low":[6,8,33],"power,":[7,34],"jitter":[9,67],"and":[10,30,48,52,65,74,81,88,97,106],"fast":[11],"Phase-Locked":[12],"Loop":[13],"(PLL).":[14],"The":[15,36,91],"main":[16],"advantages":[17],"of":[18,40,46,68,94,115,126],"the":[19,41,57,61,69,79,83,95,116,122],"proposed":[20,42,98,117],"PLL":[21,43],"are":[22,50,72,101,119],"to":[23,26,31,63],"achieve":[24],"high-speed,":[25],"generate":[27],"non-overlap":[28],"signal":[29],"consume":[32],"reliably.":[35],"total":[37],"power":[38],"consumption":[39],"in":[44,56],"frequencies":[45],"150MHz":[47,82],"400MHz":[49,80],"258.7\u03bcW":[51],"638.4\u03bcW,":[53],"respectively.":[54,90,112],"Meanwhile,":[55],"maximum":[58],"frequency":[59],"(400MHz)":[60],"pick":[62,64],"RMS":[66],"suggested":[70],"structure":[71,118],"29.95ps":[73],"8.67ps,":[75],"correspondingly.":[76],"Also,":[77],"at":[78],"locking":[84],"time":[85],"is":[86],"1.75\u03bcs":[87],"0.814\u03bcs,":[89],"active":[92],"area":[93],"PFD":[96],"charge":[99],"pump":[100],"9.16\u00d75.65\u03bcm":[102],"<sup":[103,108],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[104,109],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[105,110],"12.156.45\u03bcm":[107],",":[111],"Simulation":[113],"results":[114],"simulated":[120],"using":[121],"HSPICE":[123],"BSIM3":[124],"model":[125],"standard":[128],"0.18\u03bcm":[129],"CMOS":[130],"process.":[131]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
