{"id":"https://openalex.org/W2886117952","doi":"https://doi.org/10.23919/mixdes.2018.8436648","title":"Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology","display_name":"Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2886117952","doi":"https://doi.org/10.23919/mixdes.2018.8436648","mag":"2886117952"},"language":"en","primary_location":{"id":"doi:10.23919/mixdes.2018.8436648","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8436648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083230423","display_name":"Mikolaj Palgan","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Mikolaj Palgan","raw_affiliation_strings":["Warsaw University of Technology, Institute of Microelectronics and Optoelectronics , Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Warsaw University of Technology, Institute of Microelectronics and Optoelectronics , Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109012607","display_name":"Andrzej Pfitzner","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Andrzej Pfitzner","raw_affiliation_strings":["Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083230423"],"corresponding_institution_ids":["https://openalex.org/I108403487"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.4761634,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"299","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8285502195358276},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7527347803115845},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7343785762786865},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5246855616569519},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5195336937904358},{"id":"https://openalex.org/keywords/nor-logic","display_name":"NOR logic","score":0.504330039024353},{"id":"https://openalex.org/keywords/gate-equivalent","display_name":"Gate equivalent","score":0.48887938261032104},{"id":"https://openalex.org/keywords/multiple-emitter-transistor","display_name":"Multiple-emitter transistor","score":0.48667198419570923},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47126340866088867},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4644142985343933},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4490000009536743},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4421467185020447},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.433009535074234},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.42153671383857727},{"id":"https://openalex.org/keywords/field-effect-transistor","display_name":"Field-effect transistor","score":0.4173375964164734},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3427356481552124},{"id":"https://openalex.org/keywords/gate-oxide","display_name":"Gate oxide","score":0.3162463307380676},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2364237904548645},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21746313571929932}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.8285502195358276},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7527347803115845},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7343785762786865},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5246855616569519},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5195336937904358},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.504330039024353},{"id":"https://openalex.org/C60697091","wikidata":"https://www.wikidata.org/wiki/Q5527009","display_name":"Gate equivalent","level":5,"score":0.48887938261032104},{"id":"https://openalex.org/C66710717","wikidata":"https://www.wikidata.org/wiki/Q1952357","display_name":"Multiple-emitter transistor","level":5,"score":0.48667198419570923},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47126340866088867},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4644142985343933},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4490000009536743},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4421467185020447},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.433009535074234},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.42153671383857727},{"id":"https://openalex.org/C145598152","wikidata":"https://www.wikidata.org/wiki/Q176097","display_name":"Field-effect transistor","level":4,"score":0.4173375964164734},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3427356481552124},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.3162463307380676},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2364237904548645},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21746313571929932}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/mixdes.2018.8436648","is_oa":false,"landing_page_url":"https://doi.org/10.23919/mixdes.2018.8436648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1616249851","https://openalex.org/W1999774531","https://openalex.org/W2000428121","https://openalex.org/W2026543046","https://openalex.org/W2070771184","https://openalex.org/W2085865037","https://openalex.org/W2112813001","https://openalex.org/W2137530941","https://openalex.org/W2137978785","https://openalex.org/W2161903232","https://openalex.org/W2168635756","https://openalex.org/W2290590898","https://openalex.org/W2470243148","https://openalex.org/W2477438562","https://openalex.org/W2735678755","https://openalex.org/W2744378522","https://openalex.org/W6672422251","https://openalex.org/W6676777394","https://openalex.org/W6680745868","https://openalex.org/W6683820115","https://openalex.org/W6696841707"],"related_works":["https://openalex.org/W2760870732","https://openalex.org/W1017999001","https://openalex.org/W3210322980","https://openalex.org/W2082018612","https://openalex.org/W779139041","https://openalex.org/W2565020286","https://openalex.org/W2190122182","https://openalex.org/W2774826444","https://openalex.org/W2791832526","https://openalex.org/W2886117952"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,47,115],"part":[4],"of":[5,8,22,54,63,66,78,81,86,122,133,139,165,168],"feasibility":[6],"study":[7],"VeSTIC":[9],"(Vertical":[10],"Slit":[11],"Transistor-based":[12],"Integrated":[13],"Circuit)":[14],"technology.":[15],"The":[16,61,84],"goal":[17],"is":[18,46,172],"an":[19],"area":[20],"saving":[21],"logic":[23,124],"cells":[24],"designed":[25],"in":[26,105,114,162,174],"this":[27],"technology":[28],"by":[29,141],"using":[30],"junction-less":[31],"VeSFET":[32,140],"devices":[33],"(Vertical-Slit":[34],"Field-Effect":[35],"Transistor).":[36],"Thanks":[37],"to":[38,49,57,70,107,145,153,156],"their":[39],"feature:":[40],"two":[41,79,142],"electrically":[42],"symmetric":[43],"gates,":[44],"there":[45],"possibility":[48],"greatly":[50],"reduce":[51],"the":[52,87,119,123,134,163,166],"number":[53],"elements":[55],"required":[56],"build":[58],"digital":[59],"circuits.":[60],"use":[62],"complementary":[64],"pair":[65],"twin-gate":[67],"VeSFETs":[68],"enables":[69],"design":[71],"two-input":[72],"NOR":[73],"or":[74],"NAND":[75],"cell":[76],"composed":[77],"instead":[80],"four":[82],"transistors.":[83],"combination":[85],"key":[88],"device":[89],"parameters:":[90],"slit":[91],"width":[92],"and":[93,111,158],"dopants":[94],"concentration":[95],"as":[96,98],"well":[97],"gate":[99],"oxide":[100],"thickness":[101],"have":[102,129],"been":[103],"established":[104],"order":[106],"obtain":[108],"both":[109],"OR":[110],"AND":[112,169],"functionality":[113],"single":[116,136],"transistor,":[117],"providing":[118],"best":[120],"distinguishability":[121],"states.":[125],"In":[126],"particular,":[127],"we":[128],"confirmed":[130],"that":[131],"control":[132],"same":[135],"bulk":[137],"channel":[138],"gates":[143],"ensures":[144],"achieve":[146],"very":[147],"high":[148],"drain":[149],"current":[150],"ratio":[151],"(up":[152],"le6)":[154],"corresponding":[155],"\u201c11\u201d":[157],"\u201c10\u201d":[159],"input":[160],"states":[161],"case":[164],"transistor":[167],"functionality,":[170],"which":[171],"unattainable":[173],"other":[175],"known":[176],"technologies.":[177]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}